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answer

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Why do I receive the message "No matching files were found" in HDL Workflow Advisor Step 4.2 "Build FPGA Bitstream"?

Asked by MathWorks Support Team on 21 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
50 views

Troubleshooting connection issues with Xilinx Zynq platform

Asked by MathWorks Support Team on 3 Jul 2018

Latest activity Edited by MathWorks Support Team on 4 Mar 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

PDF Documentation for "Deep Learning HDL Toolbox Support Package for Intel / Xilinx FPGA and SoC Devices"

Asked by MathWorks Support Team on 14 Oct 2020

Latest activity Edited by MathWorks Support Team on 24 Dec 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Find Documentation, Examples and more on HDL Coder Supported Hardware in Help Center

2

answers

0 votes
4 views

Lane Detection with Zynq-Based Hardware - Pixel-Stream Model

Asked by Krishnent Sanal Kumar on 21 Jun 2018

Latest activity Answered by Eric Cigan on 18 Dec 2023

Accepted Answer by Bharath Venkataraman

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
9 views

To what degree are MathWorks drivers and libraries involved in the new ADI libiio based Linux images for Zynq + AD9361 targets?

Asked by Terje Olsen on 4 Dec 2019

Latest activity Commented on by Rimsha Javed on 7 Jun 2023

Accepted Answer by Ousman Sadiq

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

1 vote
6 views

Where I can get HDL Coder and Embedded Coder for Home license?

Asked by f1y0rdie on 11 Sep 2014

Latest activity Commented on by Xymbu on 30 Jun 2022

Accepted Answer by Shantanu Kedar

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Find Code on HDL Coder Supported Hardware in File Exchange

3

answers

0 votes
1 view

Getting Started with Targeting Xilinx Zynq Platform

Asked by Vishnu Narayan Vipin on 11 Nov 2020

Latest activity Commented on by Andrew Brennan on 17 Sep 2021

Accepted Answer by Vishnu Narayan Vipin

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

Required Linux image / utilitys for IntelSoC custom boards

Asked by Dominique Görner on 13 Jan 2020

Latest activity Commented on by JT Ferrara on 11 Feb 2021

Accepted Answer by JT Ferrara

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
2 views

error while programming hardware :device arm dap_1 is not programmable

Asked by Aravind kumar pallerla on 20 Aug 2020

Latest activity Commented on by Eduardo Flores on 29 Nov 2020

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

HDL coder and Embedded coder interaction

Asked by kimi on 14 Nov 2020

Latest activity Answered by Kiran Kintali on 15 Nov 2020

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
1 view

hdl coder supported in Cyclone 10 LP from Intel.

Asked by Iñigo Acero Urizarbarrena on 8 May 2020

Latest activity Answered by Iñigo Acero Urizarbarrena on 13 May 2020

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
3 views

Zynq Radio QPSK receiver example errors with "block_diagram does not have a parameter named 'HDLCodeGenStatus'

Asked by Neil MacEwen on 14 Aug 2019

Latest activity Answered by Neil MacEwen on 14 Aug 2019

Accepted Answer by Neil MacEwen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

How can I migrate MathWorks support on ZedBoard to Xilinx ZC702 board?

Asked by luckfy zhang on 12 Dec 2018

Latest activity Answered by Neil MacEwen on 12 Dec 2018

Accepted Answer by Neil MacEwen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
2 views

Signal measurement error when using "download"-option in HDL Workflow Advisor

Asked by Frederik Knudsen on 8 Mar 2018

Latest activity Answered by Li Qian on 17 Aug 2018

Accepted Answer by Wang Chen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

HDL Coder - Can it only Generate a project with Vivado 2107.2, not Vivado 2017.4.1

Asked by michael brewin on 25 Apr 2018

Latest activity Answered by Wang Chen on 25 Apr 2018

Accepted Answer by Wang Chen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
5 views

is it possible to run the demo "Performing Large Matrix Operation on FPGA using External Memory" on Intel Altera FPGA?

Asked by Lin Bai on 18 Feb 2018

Latest activity Commented on by Lin Bai on 10 Apr 2018

Accepted Answer by Eric Cigan

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
0 views

HDL Verifierでコシミュレーションする際のシミュレーション速度について

Asked by Shoumei on 10 Mar 2017

Latest activity Answered by Atsushi Matsumoto on 14 Mar 2017

Accepted Answer by Atsushi Matsumoto

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

XADC in simulink hdl coder

Asked by rabei shwehdi on 28 Dec 2016

Latest activity Answered by Vishal Neelagiri on 3 Jan 2017

Accepted Answer by Vishal Neelagiri

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

Create a motor controller in Simulink and compile it for an FPGA, is this possible?

Asked by Nick on 1 Sep 2015

Latest activity Answered by Cam Salzberger on 4 Sep 2015

Accepted Answer by Cam Salzberger

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
1 view

Using HDL Coder IP core in Xilinx Vivado instead of EDK

Asked by Stefan Schwarzer on 14 Jul 2014

Latest activity Commented on by Stefan Schwarzer on 14 Jul 2014

Accepted Answer by Wang Chen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

How to add Xilinx synthesis tool in the HDL Workflow advisor

Asked by Roy Francis on 25 Feb 2014

Latest activity Commented on by Roy Francis on 26 Feb 2014

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

ZedBoard full Linux for MathWorks HDL Coder

Asked by amir on 28 Nov 2013

Latest activity Commented on by amir on 3 Dec 2013

Accepted Answer by Wang Chen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

3

answers

0 votes
7 views

Problem in hdl coder

Asked by Gaurav on 9 Oct 2013

Latest activity Commented on by Gaurav on 17 Nov 2013

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

1 vote
3 views

How to create a FFT ipcore for Zynq using Simulink HDL Coder?

Asked by owen chang on 24 Sep 2013

Latest activity Commented on by owen chang on 27 Sep 2013

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Is Stateflow not supported for Xilinx HDL code generation

Asked by Wayne on 6 Jun 2013

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

HDL coder not loading simulation tool

Asked by Thomas Castle on 3 Oct 2020

Latest activity Answered by Kiran Kintali on 4 Oct 2020

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
3 views

Unable to find the software for XILINXLOGICORE

Asked by Samuel Quiniou on 6 Jan 2020

Latest activity Edited by Stefanie Schwarz on 4 Mar 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Pulse-Doppler Radar Using Xilinx RFSoC Device: HDL Workflow Advisor, setting 'AllowUnsupportedToolVersion' to 'true'.

Asked by Ahmed on 9 Aug 2023

Latest activity Commented on by Tom Mealey on 16 Aug 2023

Accepted Answer by Tom Mealey

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

3

answers

0 votes
30 views

How to avoid warnings regarding non-existent directory ?

Asked by Shravankumar P on 2 Jan 2015

Latest activity Edited by AlanO on 27 Oct 2020

Accepted Answer by Image Analyst

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
0 views

No system or file called 'axiinterfacelib' found

Asked by Yaddehi De Silva on 14 Jun 2021

Latest activity Answered by JT Ferrara on 28 Jul 2021

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
21 views

How can I use a custom board with the Zynq workflow provided by MATLAB/Simulink?

Asked by MathWorks Support Team on 17 Jul 2021

Latest activity Edited by MathWorks Support Team on 7 Jun 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
1 view

Xilinx System Generator and HDL Workflow Advisor

Asked by Sam on 30 Jan 2012

Accepted Answer by Kaustubha Govind

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Which hardware support package has linarogcctoolchain?

Asked by Vallabh on 20 Sep 2024

Latest activity Answered by Venkat Siddarth Reddy on 22 Sep 2024

Accepted Answer by Venkat Siddarth Reddy

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
1 view

Hi, I am using R2014b but cant find the HDL code in Code menu, only C/C++ code. what should i do to genarate a HDLcode for my simulink model.

Asked by SAMUDRA PANDA on 14 Dec 2021

Latest activity Commented on by SAMUDRA PANDA on 15 Dec 2021

Accepted Answer by Bharath Venkataraman

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

When I right click on a Xilinx System Generator block in Simulink, why do I get errors in MATLAB?

Asked by MathWorks Support Team on 1 Feb 2019

Latest activity Edited by MathWorks Support Team on 15 Sep 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

HDL Coder - Generate RTL Code and IP Core ERROR

Asked by Anirudh Acharya on 25 Sep 2015

Latest activity Edited by Tim McBrayer on 25 Sep 2015

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Xilinx System Generator simulink block

Asked by sameer al-obaidi on 18 Oct 2016

Latest activity Answered by Tim McBrayer on 18 Oct 2016

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

Embedded and HDL Coder Support Packages HWsetup error

Asked by Omar Aly on 24 Aug 2021

Latest activity Answered by Omar Aly on 25 Aug 2021

Accepted Answer by Omar Aly

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

1 vote
3 views

Unable to execute `ADC/DAC Loopback Data Capture' example of HDL Coder Support Package for Xilinx RFSoC Devices.

Asked by Aunullah Qaiser on 17 Jan 2022

Latest activity Answered by Praful Pai on 11 Mar 2022

Accepted Answer by Aunullah Qaiser

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

How can I modify mapping options in HDL Workflow Advisor in Simulink?

Asked by JOAQUIN GARCIA ORDOÑEZ on 21 Mar 2020

Latest activity Edited by Kiran Kintali on 22 Mar 2020

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
19 views

How to add vivado to the matlab in ubuntu/linux system?

Asked by KH on 21 Oct 2024

Latest activity Commented on by KH on 21 Oct 2024

Accepted Answer by Sahas

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
3 views

Vivado 2020.2 and HDL coder

Asked by Anonymous1 on 15 Feb 2022

Latest activity Answered by Stefanie Schwarz on 5 Dec 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

3

answers

0 votes
5 views

Can't open HDL Workflow Advisor

Asked by Ben Kistler on 3 Jun 2020

Latest activity Commented on by Ben Kistler on 3 Jun 2020

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
13 views

AD9361 Transceiver Help with FastLock Profile

Asked by William Katzianer on 5 Jun 2019

Latest activity Commented on by Neil MacEwen on 15 Jul 2019

Accepted Answer by Neil MacEwen

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

5 votes
29 views

HDL IP Core generation for Xilinx Vivado fails since the year turned from 2021 to 2022

Asked by MathWorks HDL Coder Team on 4 Jan 2022

Latest activity Commented on by Yongjie on 10 Nov 2023

Accepted Answer by MathWorks HDL Coder Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Why do I encounter an error message when I attempt to generate code for a Xilinx System Generator Subsystem?

Asked by MathWorks Support Team on 13 Dec 2016

Latest activity Answered by MathWorks Support Team on 9 Jan 2017

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

3

answers

0 votes
5 views

Error " Dot indexing is not supported for variable of this type" comes when tried to configure HDL Coder support package for Xilinx Zynq Platform.

Asked by Malhar Ashtaputre on 24 Jun 2021

Latest activity Commented on by Kiran Kintali on 4 Nov 2022

Accepted Answer by Sameer Mule

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
6 views

IP Core generation for Generic Xilinx Platform without any AXI interface

Asked by nagendra badiger on 3 May 2019

Latest activity Answered by Morris on 19 Nov 2020

Accepted Answer by nagendra badiger

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why do I get an error about a missing "thirdpartytools_win64.xml" file when I try to build my model for Xilinx Zynq platform?

Asked by MathWorks Support Team on 21 Jul 2016

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why am I getting a "SD card is read-only" error during hardware setup for HDL Verifier Support Package for Xilinx FPGA Boards?

Asked by MathWorks Support Team on 10 Jan 2024

Latest activity Answered by MathWorks Support Team on 19 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

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