I am trying to use parameterized macros in Verilog to dynamically change the master module of instances through macro names as tried below.
`define AND_CELL(tech) ``tech``_2oi1_1x
`define TECH_1 tech1
`define TECH_2 tech2
module top(in1, in2, in3, in4, out_x);
input in1, in2, in3, in4;
output out_x;
wire t1_c, t2_c;
`AND_CELL(`TECH_1) u1(.a(in1), .b(in2), .x(t1_c));
`AND_CELL(`TECH_2) u2(.a(in3), .b(in4), .x(t2_c));
assign out_x = t1_c | t2_c ;
endmodule
module tech1_2oi1_1x(a, b, x);
input a, b;
output x;
assign x = a & b;
endmodule
module tech2_2oi1_1x(a, b, x);
input a, b;
output x;
assign x = a & b;
endmodule
The intent here to have the top module to have two different AND gates based on the TECH_1 and TECH_2 macro values, which can be changed design to design.
Your question is not very clear. There is no such thing as a parameterized macro in SystemVerilog. What you are showing is a macro with arguments. Macros expand their text as the compiler reads the source file. Verilog parameters are a special kind of constant that is evaluated at elaboration(flattening), and can be overridden on an instance by instance basis. Macros get expanded before the compiler understands what constructs it is dealing with, followed by elaboration of parameters. You can’t dynamically change either one of them because “dynamic” implies while the simulation is running.
If you have different designs, you can certainly change the definitions of `defines TECH_1 and TECH_2 before compiling each design. But if you have two instances of the same designs in the same simulation, and want them to use different technologies, using macros will not work. What you need to do in that case is a have two different libraries and use the same module names in both. The you can select which libraries you want to use for each instance.
You need to clarify what you are looking to do before I can spend more time answering your question.