This is typical behavior when generating VHDL code for a subsystem. By default, the generated model inserts delays in the model to account for hardware implementation on an FPGA. Notice the output in the Command Window upon generating code from such a subsystem:
### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 23 cycles.
When the HDL code is implemented in hardware, we cannot expect correctly computed values until after a certain amount of time steps. In the attached example, notice that increasing the simulation time to 50 seconds and then generating HDL code will result in a generated model that will show the expected output after 23 cycles have elapsed.
