diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index 7cdc1022ca..2894a094f9 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -48,7 +48,13 @@ "GENERIC_C031C4UX", "GENERIC_C031C6TX", "GENERIC_C031F4PX", + "GENERIC_C071G8UX", "GENERIC_C071R8TX", + "GENERIC_C092CBTX", + "GENERIC_C092CBUX", + "GENERIC_C092CCTX", + "GENERIC_C092RBTX", + "GENERIC_C092RCIX", "GENERIC_F031C4TX", "GENERIC_F031E6YX", "GENERIC_F031F4PX", @@ -240,6 +246,7 @@ "GENERIC_F411CCYX", "GENERIC_F411CEUX", "GENERIC_F411RCTX", + "GENERIC_F411VCTX", "GENERIC_F412CEUX", "GENERIC_F412RETX", "GENERIC_F412REYX", @@ -835,12 +842,19 @@ "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U073C8TX", + "GENERIC_U073C8UX", + "GENERIC_U073CBTX", + "GENERIC_U073CBUX", + "GENERIC_U073CCTX", + "GENERIC_U073CCUX", "GENERIC_U073R8IX", "GENERIC_U073R8TX", "GENERIC_U073RBIX", "GENERIC_U073RBTX", "GENERIC_U073RCIX", "GENERIC_U073RCTX", + "GENERIC_U083CCTX", "GENERIC_U083RCIX", "GENERIC_U375RETXQ", "GENERIC_U375RGTXQ", @@ -857,6 +871,14 @@ "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", "GENERIC_U585CITX", + "GENERIC_U595ZITXQ", + "GENERIC_U595ZJTXQ", + "GENERIC_U599ZITXQ", + "GENERIC_U599ZJTXQ", + "GENERIC_U5A5ZJTXQ", + "GENERIC_WB05KZVX", + "GENERIC_WB05TZFX", + "GENERIC_WB09KEVX", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", @@ -870,6 +892,11 @@ "GENERIC_WB55VGQX", "GENERIC_WB55VGYX", "GENERIC_WBA55CEUX", + "GENERIC_WL33C8VX", + "GENERIC_WL33C8VXX", + "GENERIC_WL33CBVX", + "GENERIC_WL33CBVXX", + "GENERIC_WL33CCVX", "GENERIC_WL54CCUX", "GENERIC_WL54JCIX", "GENERIC_WL55CCUX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index 267c32f85c..02d9a341d4 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -48,7 +48,13 @@ "GENERIC_C031C4UX", "GENERIC_C031C6TX", "GENERIC_C031F4PX", + "GENERIC_C071G8UX", "GENERIC_C071R8TX", + "GENERIC_C092CBTX", + "GENERIC_C092CBUX", + "GENERIC_C092CCTX", + "GENERIC_C092RBTX", + "GENERIC_C092RCIX", "GENERIC_F031C4TX", "GENERIC_F031E6YX", "GENERIC_F031F4PX", @@ -240,6 +246,7 @@ "GENERIC_F411CCYX", "GENERIC_F411CEUX", "GENERIC_F411RCTX", + "GENERIC_F411VCTX", "GENERIC_F412CEUX", "GENERIC_F412RETX", "GENERIC_F412REYX", @@ -835,12 +842,19 @@ "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U073C8TX", + "GENERIC_U073C8UX", + "GENERIC_U073CBTX", + "GENERIC_U073CBUX", + "GENERIC_U073CCTX", + "GENERIC_U073CCUX", "GENERIC_U073R8IX", "GENERIC_U073R8TX", "GENERIC_U073RBIX", "GENERIC_U073RBTX", "GENERIC_U073RCIX", "GENERIC_U073RCTX", + "GENERIC_U083CCTX", "GENERIC_U083RCIX", "GENERIC_U375RETXQ", "GENERIC_U375RGTXQ", @@ -857,6 +871,14 @@ "GENERIC_U575ZGTXQ", "GENERIC_U575ZITXQ", "GENERIC_U585CITX", + "GENERIC_U595ZITXQ", + "GENERIC_U595ZJTXQ", + "GENERIC_U599ZITXQ", + "GENERIC_U599ZJTXQ", + "GENERIC_U5A5ZJTXQ", + "GENERIC_WB05KZVX", + "GENERIC_WB05TZFX", + "GENERIC_WB09KEVX", "GENERIC_WB35CCUXA", "GENERIC_WB35CEUXA", "GENERIC_WB55CCUX", @@ -870,6 +892,11 @@ "GENERIC_WB55VGQX", "GENERIC_WB55VGYX", "GENERIC_WBA55CEUX", + "GENERIC_WL33C8VX", + "GENERIC_WL33C8VXX", + "GENERIC_WL33CBVX", + "GENERIC_WL33CBVXX", + "GENERIC_WL33CCVX", "GENERIC_WL54CCUX", "GENERIC_WL54JCIX", "GENERIC_WL55CCUX", diff --git a/CI/update/patch/CMSIS/WL3/0001-feat-wl3-add-__libc_init_array-call-to-startup.patch b/CI/update/patch/CMSIS/WL3/0001-feat-wl3-add-__libc_init_array-call-to-startup.patch new file mode 100644 index 0000000000..3323401377 --- /dev/null +++ b/CI/update/patch/CMSIS/WL3/0001-feat-wl3-add-__libc_init_array-call-to-startup.patch @@ -0,0 +1,26 @@ +From d4316ffbdd8fb8eb5863d9198422b832aafd44c6 Mon Sep 17 00:00:00 2001 +From: Frederic Pillon +Date: Tue, 23 Sep 2025 09:50:23 +0200 +Subject: [PATCH 1/1] feat(wl3): add __libc_init_array call to startup + +Signed-off-by: Frederic Pillon +--- + .../ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s +index 68b8c7ab4..28bf2e6da 100644 +--- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s ++++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s +@@ -83,6 +83,8 @@ LoopFillZerobss: + cmp r2, r3 + bcc FillZerobss + ++/* Call static constructors */ ++ bl __libc_init_array + /* Call the application's entry point.*/ + bl main + +-- +2.34.1 + diff --git a/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch b/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch new file mode 100644 index 0000000000..9c4c0d7601 --- /dev/null +++ b/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch @@ -0,0 +1,877 @@ +From 6d24d07674b242544e2f24a26dd9785efb178650 Mon Sep 17 00:00:00 2001 +From: Frederic Pillon +Date: Tue, 23 Sep 2025 14:48:50 +0200 +Subject: [PATCH 1/1] fix(wl3): HAL and LL warnings + +Signed-off-by: Frederic Pillon +--- + .../Inc/stm32wl3x_ll_dma.h | 104 ++++++++++++++++++ + .../Src/stm32wl3x_hal_flash_ex.c | 2 +- + .../Src/stm32wl3x_ll_adc.c | 2 +- + 3 files changed, 106 insertions(+), 2 deletions(-) + +diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +index b94790b32..e49d7c53f 100644 +--- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h ++++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +@@ -433,6 +433,7 @@ typedef struct + */ + __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); + } + +@@ -453,6 +454,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); + } + +@@ -473,6 +475,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); + } +@@ -509,6 +512,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +@@ -536,6 +540,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, + */ + __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); + } +@@ -561,6 +566,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t + */ + __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + } +@@ -587,6 +593,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint + */ + __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, + Mode); + } +@@ -610,6 +617,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ + */ + __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_CIRC)); + } +@@ -634,6 +642,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); + } +@@ -657,6 +666,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_PINC)); + } +@@ -681,6 +691,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); + } +@@ -704,6 +715,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_MINC)); + } +@@ -729,6 +741,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); + } +@@ -753,6 +766,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u + */ + __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_PSIZE)); + } +@@ -778,6 +792,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe + */ + __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); + } +@@ -802,6 +817,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u + */ + __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_MSIZE)); + } +@@ -828,6 +844,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe + */ + __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, + Priority); + } +@@ -853,6 +870,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t + */ + __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_PL)); + } +@@ -877,6 +895,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 + */ + __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, + DMA_CNDTR_NDT, NbData); + } +@@ -900,6 +919,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u + */ + __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, + DMA_CNDTR_NDT)); + } +@@ -931,6 +951,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe + __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) + { ++ (void)DMAx; + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { +@@ -965,6 +986,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, + */ + __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) + { ++ (void)DMAx; + WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); + } + +@@ -988,6 +1010,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) + { ++ (void)DMAx; + WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); + } + +@@ -1009,6 +1032,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); + } + +@@ -1030,6 +1054,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); + } + +@@ -1053,6 +1078,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) + { ++ (void)DMAx; + WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); + } + +@@ -1076,6 +1102,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) + { ++ (void)DMAx; + WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); + } + +@@ -1097,6 +1124,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); + } + +@@ -1118,6 +1146,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); + } + +@@ -1140,6 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) + { ++ (void)DMAx; + MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); + } + +@@ -1161,6 +1191,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel + */ + __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); + } + +@@ -1180,6 +1211,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); + } + +@@ -1191,6 +1223,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); + } + +@@ -1202,6 +1235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); + } + +@@ -1213,6 +1247,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); + } + +@@ -1224,6 +1259,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); + } + +@@ -1235,6 +1271,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); + } + +@@ -1246,6 +1283,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); + } + +@@ -1257,6 +1295,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); + } + +@@ -1268,6 +1307,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); + } + +@@ -1279,6 +1319,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); + } + +@@ -1290,6 +1331,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); + } + +@@ -1301,6 +1343,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); + } + +@@ -1312,6 +1355,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); + } + +@@ -1323,6 +1367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); + } + +@@ -1334,6 +1379,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); + } + +@@ -1345,6 +1391,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); + } + +@@ -1356,6 +1403,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); + } + +@@ -1367,6 +1415,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); + } + +@@ -1378,6 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); + } + +@@ -1389,6 +1439,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); + } + +@@ -1400,6 +1451,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); + } + +@@ -1411,6 +1463,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); + } + +@@ -1422,6 +1475,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); + } + +@@ -1433,6 +1487,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); + } + +@@ -1444,6 +1499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); + } + +@@ -1455,6 +1511,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); + } + +@@ -1466,6 +1523,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); + } + +@@ -1477,6 +1535,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); + } + +@@ -1488,6 +1547,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); + } + +@@ -1499,6 +1559,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); + } + +@@ -1510,6 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); + } + +@@ -1521,6 +1583,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); + } + +@@ -1532,6 +1595,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); + } + +@@ -1543,6 +1607,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); + } + +@@ -1554,6 +1619,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); + } + +@@ -1565,6 +1631,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); + } + +@@ -1576,6 +1643,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); + } + +@@ -1587,6 +1655,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); + } + +@@ -1598,6 +1667,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); + } + +@@ -1609,6 +1679,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); + } + +@@ -1620,6 +1691,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); + } + +@@ -1631,6 +1703,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); + } + +@@ -1642,6 +1715,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); + } + +@@ -1653,6 +1727,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); + } + +@@ -1664,6 +1739,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); + } + +@@ -1675,6 +1751,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); + } + +@@ -1686,6 +1763,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); + } + +@@ -1697,6 +1775,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); + } + +@@ -1708,6 +1787,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); + } + +@@ -1719,6 +1799,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); + } + +@@ -1730,6 +1811,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); + } + +@@ -1741,6 +1823,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); + } + +@@ -1752,6 +1835,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); + } + +@@ -1763,6 +1847,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); + } + +@@ -1774,6 +1859,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); + } + +@@ -1785,6 +1871,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); + } + +@@ -1796,6 +1883,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); + } + +@@ -1807,6 +1895,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); + } + +@@ -1818,6 +1907,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); + } + +@@ -1829,6 +1919,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); + } + +@@ -1840,6 +1931,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); + } + +@@ -1851,6 +1943,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); + } + +@@ -1862,6 +1955,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); + } + +@@ -1873,6 +1967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) + { ++ (void)DMAx; + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); + } + +@@ -1900,6 +1995,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) + */ + __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); + } + +@@ -1920,6 +2016,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); + } + +@@ -1940,6 +2037,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); + } + +@@ -1960,6 +2058,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); + } + +@@ -1980,6 +2079,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); + } + +@@ -2000,6 +2100,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); + } + +@@ -2020,6 +2121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) + */ + __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); + } +@@ -2041,6 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann + */ + __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); + } +@@ -2062,6 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann + */ + __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) + { ++ (void)DMAx; + return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); + } +diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c +index 9cd95caf3..d1b9f3dd0 100644 +--- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c ++++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c +@@ -107,7 +107,7 @@ static void FLASH_Program_OTPWord(uint32_t Address, uint32_t Data); + */ + HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) + { +- HAL_StatusTypeDef status; ++ HAL_StatusTypeDef status = HAL_ERROR; + uint32_t index; + + /* Check the parameters */ +diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c +index 5455a5343..4a88375ed 100644 +--- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c ++++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c +@@ -24,7 +24,7 @@ + #ifdef USE_FULL_ASSERT + #include "stm32_assert.h" + #else +-#define assert_param(expr) ((void)0UL) ++#define assert_param(expr) ((void)0U) + #endif /* USE_FULL_ASSERT */ + + /** @addtogroup STM32WL3x_LL_Driver +-- +2.34.1 + diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index eb2a08f337..5cea6cd56f 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -707,8 +707,8 @@ def dac_pinmap(): def i2c_pinmap(lst): i2c_pins_list = [] - winst = [] - wpin = [] + winst = [0] + wpin = [0] mode = "STM_MODE_AF_OD" if lst == i2csda_list: aname = "I2C_SDA" @@ -1651,7 +1651,7 @@ def search_product_line(valueline: str, extra: str) -> str: for idx_pline, pline in enumerate(product_line_list): vline = valueline product_line = pline - if vline.startswith("STM32WB0"): + if vline.startswith("STM32WB0") or vline.startswith("STM32WL3"): pline = pline + "xx" # Remove the 'x' character from pline and # the one at same index in the vline @@ -2153,7 +2153,7 @@ def keyflash(x): return x[0] -def group_by_flash(group_base_list, glist, index_mcu_base): +def group_by_flash(glist, index_mcu_base): expanded_dir_list = [] group_flash_list = [] new_mcu_dirname = "" @@ -2204,15 +2204,19 @@ def group_by_flash(group_base_list, glist, index_mcu_base): ext_list = [] for ppe in key_package_list: sub = mcu_PE_regex.search(ppe) - package_list.append(sub.group(1)) - # Assert - if sub.group(2) != "x": - print( - f"Package of {base_name}, ppe {ppe} info contains {sub.group(2)} instead of 'x'" - ) + if not sub: + print(f"Package: {base_name}, ppe: {ppe} not recognized") exit(1) - if sub.group(3): - ext_list.append(sub.group(3)) + else: + package_list.append(sub.group(1)) + # Assert + if sub.group(2) != "x": + print( + f"Package: {base_name}, ppe: {ppe} contains {sub.group(2)} instead of 'x'" + ) + exit(1) + if sub.group(3): + ext_list.append(sub.group(3)) # Count each subpart pcounter = Counter(package_list) ecounter = Counter(ext_list) @@ -2237,7 +2241,7 @@ def group_by_flash(group_base_list, glist, index_mcu_base): return new_mcu_dirname -def merge_dir(out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp): +def merge_dir(out_temp_path, group_mcu_dir, mcu_family_name, periph_xml, variant_exp): dirname_list = [] new_mcu_dirname = "" # Working mcu directory @@ -2245,9 +2249,11 @@ def merge_dir(out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp) # Merge if needed if len(group_mcu_dir) != 1: # Handle mcu name length dynamically - # Add 3 for extra information line, #pin and flash - index_mcu_base = len(mcu_family.name.removeprefix("STM32").removesuffix(nx)) + 3 - + # Add num for extra information line, #pin and flash + nx = stm32_dict[mcu_family_name.removeprefix("STM32")] + index_mcu_base = len(mcu_family_name.removeprefix("STM32").removesuffix(nx)) + ( + 3 if len(nx) == 2 else 2 + ) # Extract only dir name for dir_name in group_mcu_dir: dirname_list.append(dir_name.stem) @@ -2266,14 +2272,14 @@ def merge_dir(out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp) new_mcu_dirname += f"{'_' if index != 0 else ''}{glist[0].strip('x')}" else: # Group using flash info - gbf = group_by_flash(group_base_list, glist, index_mcu_base) + gbf = group_by_flash(glist, index_mcu_base) new_mcu_dirname += f"{'_' if index != 0 else ''}{gbf}" del group_package_list[:] del group_flash_list[:] del group_base_list[:] del dirname_list[:] - new_mcu_dir = out_temp_path / mcu_family.name / new_mcu_dirname + new_mcu_dir = out_temp_path / f"{mcu_family_name}{nx}" / new_mcu_dirname board_entry = "" with open(mcu_dir / boards_entry_filename) as fp: @@ -2366,10 +2372,11 @@ def aggregate_dir(): # Compare per family for mcu_family_name in aggregate_serie_list: - mcu_family = out_temp_path / f"{mcu_family_name}{nx}" - out_family_path = root_dir / "variants" / mcu_family.name + nx = stm32_dict[mcu_family_name.removeprefix("STM32")] + mcu_family_path = out_temp_path / f"{mcu_family_name}{nx}" + out_family_path = root_dir / "variants" / mcu_family_path.name # Get all mcu_dir - mcu_dirs = sorted(mcu_family.glob("*/")) + mcu_dirs = sorted(mcu_family_path.glob("*/")) # Get original directory list of current serie STM32YYxx mcu_out_dirs_ori = sorted(out_family_path.glob("*/**")) mcu_out_dirs_up = [] @@ -2432,7 +2439,7 @@ def aggregate_dir(): # Merge directories name and contents if needed mcu_dir = merge_dir( - out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp + out_temp_path, group_mcu_dir, mcu_family_name, periph_xml, variant_exp ) # Move to variants/ folder out_path = out_family_path / mcu_dir.stem @@ -2455,7 +2462,7 @@ def aggregate_dir(): if new_dirs: nb_new = len(new_dirs) dir_str = "directories" if nb_new > 1 else "directory" - print(f"\nNew {dir_str} for {mcu_family.name}:\n") + print(f"\nNew {dir_str} for {mcu_family_path.name}:\n") for d in new_dirs: print(f" - {d.name}") print("\n --> Please, check if it is a new directory or a renamed one.") @@ -2463,7 +2470,7 @@ def aggregate_dir(): if old_dirs: nb_old = len(old_dirs) dir_str = "Directories" if nb_old > 1 else "Directory" - print(f"\n{dir_str} not updated for {mcu_family.name}:\n") + print(f"\n{dir_str} not updated for {mcu_family_path.name}:\n") for d in old_dirs: # Check if ldsript.ld file exists in the folder if not (d / "ldscript.ld").exists(): diff --git a/CI/update/stm32wrapper.py b/CI/update/stm32wrapper.py index 1abdba4c1c..7c85db0cb1 100644 --- a/CI/update/stm32wrapper.py +++ b/CI/update/stm32wrapper.py @@ -61,7 +61,7 @@ # re peripheral_c_regex = re.compile(r"stm32\w+_[h]?[al][l]_(.*).c$") -peripheral_h_regex = re.compile(r"stm32\w+_(\w+).h$") +peripheral_h_regex = re.compile(r"stm32\w+_[h]?[al][l]_(.*).h$") def checkConfig(arg_core, arg_cmsis): diff --git a/README.md b/README.md index c9377b8e62..323704d3f7 100644 --- a/README.md +++ b/README.md @@ -78,6 +78,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d - [Generic STM32WB boards](#generic-stm32wb-boards) - [Generic STM32WB0 boards](#generic-stm32wb0-boards) - [Generic STM32WBA boards](#generic-stm32wba-boards) + - [Generic STM32WL3 boards](#generic-stm32wl3-boards) - [Generic STM32WL boards](#generic-stm32wl-boards) - [3D printer boards](#3d-printer-boards) - [Blues boards](#blues-boards) @@ -114,6 +115,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H563ZI | [Nucleo H563ZI](https://www.st.com/en/evaluation-tools/nucleo-h563zi.html) | *2.6.0* | | | :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | | | :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 | +| :yellow_heart: | STM32H745ZI-Q | [Nucleo-H745ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html) | **2.12.0** | | | :green_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | *2.7.0* | | | :green_heart: | STM32H7A3ZITxQ | [NUCLEO-H7A3ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html) | *2.10.0* | | | :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | | @@ -138,6 +140,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F103RB | [Nucleo F103RB](http://www.st.com/en/evaluation-tools/nucleo-f103rb.html) | *0.2.0* | | | :green_heart: | STM32F302R8 | [Nucleo F302R8](http://www.st.com/en/evaluation-tools/nucleo-f302r8.html) | *1.1.0* | | | :green_heart: | STM32F303RE | [Nucleo F303RE](http://www.st.com/en/evaluation-tools/nucleo-f303re.html) | *0.1.0* | | +| :yellow_heart: | STM32F334R8 | [Nucleo-F334R8](https://www.st.com/en/evaluation-tools/nucleo-f334r8.html) | **2.12.0** | | | :green_heart: | STM32F401RE | [Nucleo F401RE](http://www.st.com/en/evaluation-tools/nucleo-f401re.html) | *0.2.1* | | | :green_heart: | STM32F410RB | [Nucleo F410RB](http://www.st.com/en/evaluation-tools/nucleo-f410rb.html) | *2.11.0* | | | :green_heart: | STM32F411RE | [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) | *0.2.1* | | @@ -164,6 +167,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32WBA55CGU | Nucleo-WBA55CG | *2.8.0* | | | :green_heart: | STM32WB55RG | [P-Nucleo-WB55RG](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) | *1.6.0* | BLE support with [STM32duinoBLE](https://github.com/stm32duino/STM32duinoBLE) | | :green_heart: | STM32WB55CG | [P-Nucleo-WB55 USB Dongle](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) | *2.5.0* | BLE support with [STM32duinoBLE](https://github.com/stm32duino/STM32duinoBLE) | +| :yellow_heart: | STM32WL3CCV | [Nucleo-WL33CC1](https://www.st.com/en/evaluation-tools/nucleo-wl33cc1.html) | **2.12.0** | | +| :yellow_heart: | STM32WL3CCV | [Nucleo-WL33CC2](https://www.st.com/en/evaluation-tools/nucleo-wl33cc2.html) | **2.12.0** | | | :green_heart: | STM32WL55JC | [Nucleo WL55JC1](https://www.st.com/en/evaluation-tools/nucleo-wl55jc.html) | *2.1.0* | LoRa support not available | @@ -191,7 +196,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F100RB | [STM32VLDISCOVERY](https://www.st.com/en/evaluation-tools/stm32vldiscovery.html) | 0.2.1 | | | :green_heart: | STM32F303VC | [STM32F3DISCOVERY](https://www.st.com/en/evaluation-tools/stm32f3discovery.html) | *2.0.0* | | | :green_heart: | STM32F407VG | [STM32F407G-DISC1](http://www.st.com/en/evaluation-tools/stm32f4discovery.html) | *0.1.0* | | +| :yellow_heart: | STM32F411VE | [STM32F411E-DISCO](https://www.st.com/en/evaluation-tools/32f411ediscovery.html) | **2.12.0** | | | :green_heart: | STM32F413ZH | [32F413HDISCOVERY](https://www.st.com/en/evaluation-tools/32f413hdiscovery.html) | *1.9.0* | | +| :yellow_heart: | STM32F429I | [STM32F429I-DISC1](https://www.st.com/en/evaluation-tools/32f429idiscovery.html) | **2.12.0** | | | :green_heart: | STM32F746NG | [STM32F746G-DISCOVERY](http://www.st.com/en/evaluation-tools/32f746gdiscovery.html) | *0.1.0* | | | :green_heart: | STM32G031J6 | [STM32G0316-DISCO](https://www.st.com/en/evaluation-tools/stm32g0316-disco.html) | *1.9.0* | | | :green_heart: | STM32G431CB | [B-G431B-ESC1](https://www.st.com/en/evaluation-tools/b-g431b-esc1.html) | *2.0.0* | | @@ -225,9 +232,10 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32C011J4
STM32C011J6 | Generic Board | *2.8.0* | | | :green_heart: | STM32C031C4
STM32C031C6 | Generic Board | *2.5.0* | | | :green_heart: | STM32C031F4
STM32C031F6 | Generic Board | *2.6.0* | | +| :yellow_heart: | STM32C051C6
STM32C051C8 | Generic Board | **2.12.0** | | | :green_heart: | STM32C071G8
STM32C071GB | Generic Board | *2.11.0* | | | :green_heart: | STM32C071R8
STM32C071RB | Generic Board | *2.9.0* | | -| :green_heart: | STM32C092CBT | Generic Board | *2.11.0* | | +| :yellow_heart: | STM32C092CB
STM32C092CC| Generic Board | **2.12.0** | STM32C092CBT since 2.11.0 | | :green_heart: | STM32C092RBT
STM32C092RCT | Generic Board | *2.11.0* | | | :green_heart: | STM32C092RCI | Generic Board | *2.11.0* | | @@ -303,6 +311,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F101ZC
STM32F101ZD
STM32F101ZE | Generic Board | *2.4.0* | | | :green_heart: | STM32F103C6
STM32F103C8
STM32F103CB | [Blue Pill](https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill) | *1.2.0* | USB CDC support since *1.5.0*
Maple bootloaders support since *1.6.0* | | :green_heart: | STM32F103C8
STM32F103CB | [Black Pill](https://stm32-base.org/boards/STM32F103C8T6-Black-Pill) | *1.5.0* | | +| :yellow_heart: | STM32F103C8 | [Databoard](https://github.com/its-kronos/Databoard) | **2.12.0** | | | :green_heart: | STM32F103C4
STM32F103C6
STM32F103C8
STM32F103CB | Generic Board | *1.9.0* | | | :green_heart: | STM32F103R8
STM32F103RB
STM32F103RC
STM32F103RE | [Blue Button F103Rx](https://stm32-base.org/boards/STM32F103RET6-Generic-Board) | *1.9.0* | | | :green_heart: | STM32F103R6
STM32F103R8
STM32F103RB
STM32F103RC
STM32F103RD
STM32F103RE
STM32F103RF
STM32F103RG | Generic Board | *1.9.0* | | @@ -389,6 +398,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F410T8
STM32F410TB | Generic Board | *2.4.0* | | | :green_heart: | STM32F411CC
STM32F411CE | Generic Board | *1.9.0* | | | :green_heart: | STM32F411RC
STM32F411RE | Generic Board | *1.9.0* | | +| :yellow_heart: | STM32F411VC
STM32F411VE | Generic Board | **2.12.0** | | | :green_heart: | STM32F412CE
STM32F412CG | Generic Board | *1.9.0* | | | :green_heart: | STM32F412RE
STM32F412RG | Generic Board | *1.9.0* | | | :green_heart: | STM32F412ZE
STM32F412ZG | Generic Board | *2.6.0* | | @@ -586,7 +596,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | +| :yellow_heart: | STM32H723VE
STM32H723VG | Generic Board | **2.12.0** | | | :green_heart: | STM32H723ZE
STM32H723ZG | Generic Board | *2.4.0* | | +| :yellow_heart: | STM32H730VB
STM32H733VGT | Generic Board | **2.12.0** | | | :green_heart: | STM32H730ZBT | Generic Board | *2.4.0* | | | :green_heart: | STM32H733ZGT | Generic Board | *2.4.0* | | | :green_heart: | STM32H742IG
STM32H742II | Generic Board | *2.1.0* | | @@ -600,6 +612,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H743XG
STM32H743XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H743ZG
STM32H743ZI | Generic Board | *2.0.0* | | | :green_heart: | STM32H745XG
STM32H745XI | Generic Board | *2.7.0* | | +| :yellow_heart: | STM32H745ZG
STM32H745ZI | Generic Board | **2.12.0** | | | :green_heart: | STM32H747AG
STM32H747AI | Generic Board | *2.0.0* | | | :green_heart: | STM32H747IG
STM32H747II | Generic Board | *2.0.0* | | | :green_heart: | STM32H747XG
STM32H747XI | Generic Board | *2.7.0* | | @@ -616,6 +629,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H753XI | Generic Board | *2.7.0* | | | :green_heart: | STM32H753ZI | Generic Board | *2.0.0* | | | :green_heart: | STM32H755XI | Generic Board | *2.7.0* | | +| :yellow_heart: | STM32H755ZI | Generic Board | **2.12.0** | | | :green_heart: | STM32H757AI | Generic Board | *2.0.0* | | | :green_heart: | STM32H757II | Generic Board | *2.0.0* | | | :green_heart: | STM32H757XI | Generic Board | *2.7.0* | | @@ -817,6 +831,13 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32WBA55CEU
STM32WBA55CGU | Generic Board | *2.8.0* | | +### Generic STM32WL3 boards + +| Status | Device(s) | Name | Release | Notes | +| :----: | :-------: | ---- | :-----: | :---- | +| :yellow_heart: | STM32WL3C8V
STM32WL3CBV
STM32WL3CCV | Generic Board | **2.12.0** | | +| :yellow_heart: | STM32WL3C8VX
STM32WL3CBVX
STM32WL3CCVX | Generic Board | **2.12.0** | | + ### Generic STM32WL boards | Status | Device(s) | Name | Release | Notes | diff --git a/boards.txt b/boards.txt index 17d2769d65..1666e5edb5 100644 --- a/boards.txt +++ b/boards.txt @@ -257,6 +257,24 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant_h=variant_NUCLEO_H743ZI.h Nucleo_144.menu.pnum.NUCLEO_H743ZI2.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H743ZI2.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd +# NUCLEO_H745ZI_Q board +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q=Nucleo H745ZI-Q +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.node=NODE_H743ZIQ +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.upload.maximum_size=2097152 +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.upload.maximum_data_size=884736 +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.mcu=cortex-m7 +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.float-abi=-mfloat-abi=hard +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -DCORE_CM7 +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.board=NUCLEO_H745ZI_Q +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.series=STM32H7xx +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.product_line=STM32H745xx +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.variant_h=variant_NUCLEO_H745ZI_Q.h +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.openocd.target=stm32h7x +Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd + + # NUCLEO_H753ZI board Nucleo_144.menu.pnum.NUCLEO_H753ZI=Nucleo H753ZI Nucleo_144.menu.pnum.NUCLEO_H753ZI.node=NODE_H753ZI @@ -403,22 +421,22 @@ Nucleo_144.menu.upload_method.MassStorage.upload.tool=massStorageCopy Nucleo_144.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Nucleo_144.menu.upload_method.swdMethod.upload.protocol=swd -Nucleo_144.menu.upload_method.swdMethod.upload.options= +Nucleo_144.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Nucleo_144.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Nucleo_144.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Nucleo_144.menu.upload_method.jlinkMethod.upload.protocol=jlink -Nucleo_144.menu.upload_method.jlinkMethod.upload.options= +Nucleo_144.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Nucleo_144.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Nucleo_144.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Nucleo_144.menu.upload_method.serialMethod.upload.protocol=serial -Nucleo_144.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +Nucleo_144.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} Nucleo_144.menu.upload_method.serialMethod.upload.tool=stm32CubeProg Nucleo_144.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Nucleo_144.menu.upload_method.dfuMethod.upload.protocol=dfu -Nucleo_144.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Nucleo_144.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Nucleo_144.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Nucleo_144.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -501,7 +519,7 @@ Nucleo_64.menu.pnum.NUCLEO_C092RC.build.mcu=cortex-m0plus Nucleo_64.menu.pnum.NUCLEO_C092RC.build.board=NUCLEO_C092RC Nucleo_64.menu.pnum.NUCLEO_C092RC.build.series=STM32C0xx Nucleo_64.menu.pnum.NUCLEO_C092RC.build.product_line=STM32C092xx -Nucleo_64.menu.pnum.NUCLEO_C092RC.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +Nucleo_64.menu.pnum.NUCLEO_C092RC.build.variant=STM32C0xx/C092RBT_C092RC(I-T) Nucleo_64.menu.pnum.NUCLEO_C092RC.build.st_extra_flags=-DSTM32C092xx {build.xSerial} -D__CORTEX_SC=0 Nucleo_64.menu.pnum.NUCLEO_C092RC.openocd.target=stm32c0x Nucleo_64.menu.pnum.NUCLEO_C092RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd @@ -601,6 +619,21 @@ Nucleo_64.menu.pnum.NUCLEO_F303RE.build.variant=STM32F3xx/F303R(D-E)T Nucleo_64.menu.pnum.NUCLEO_F303RE.openocd.target=stm32f3x Nucleo_64.menu.pnum.NUCLEO_F303RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F303.svd +# NUCLEO_F334R8 board +Nucleo_64.menu.pnum.NUCLEO_F334R8=Nucleo F334R8 +Nucleo_64.menu.pnum.NUCLEO_F334R8.node=NODE_F334R8 +Nucleo_64.menu.pnum.NUCLEO_F334R8.upload.maximum_size=65536 +Nucleo_64.menu.pnum.NUCLEO_F334R8.upload.maximum_data_size=12288 +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.mcu=cortex-m4 +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.float-abi=-mfloat-abi=hard +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.board=NUCLEO_F334R8 +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.series=STM32F3xx +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.product_line=STM32F334x8 +Nucleo_64.menu.pnum.NUCLEO_F334R8.build.variant=STM32F3xx/F303R(6-8)T_F334R(6-8)T +Nucleo_64.menu.pnum.NUCLEO_F334R8.openocd.target=stm32f3x +Nucleo_64.menu.pnum.NUCLEO_F334R8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F334.svd + # NUCLEO_F401RE board Nucleo_64.menu.pnum.NUCLEO_F401RE=Nucleo F401RE Nucleo_64.menu.pnum.NUCLEO_F401RE.node="NODE_F401RE,NUCLEO" @@ -905,7 +938,7 @@ Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.build.series=STM32U3xx Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.build.product_line=STM32U385xx Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ #Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.openocd.target=stm32u3x -#Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +#Nucleo_64.menu.pnum.NUCLEO_U385RG_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # NUCLEO_WB09KE board Nucleo_64.menu.pnum.NUCLEO_WB09KE=Nucleo WB09KE @@ -923,6 +956,7 @@ Nucleo_64.menu.pnum.NUCLEO_WB09KE.debug.svd_file={runtime.tools.STM32_SVD.path}/ Nucleo_64.menu.pnum.NUCLEO_WB09KE.upload.address=0x10040000 Nucleo_64.menu.pnum.NUCLEO_WB09KE.upload.mode=hwRstPulse Nucleo_64.menu.pnum.NUCLEO_WB09KE.upload.start=0x10000000 +Nucleo_64.menu.pnum.NUCLEO_WB09KE.upload.parity=none # NUCLEO_WB15CC Nucleo_64.menu.pnum.NUCLEO_WB15CC=Nucleo WB15CC @@ -984,6 +1018,44 @@ Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.variant=STM32WBAxx/WBA55C(E-G)U Nucleo_64.menu.pnum.NUCLEO_WBA55CG.openocd.target=stm32wbax Nucleo_64.menu.pnum.NUCLEO_WBA55CG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBAxx/STM32WBA55.svd +# NUCLEO_WL3CC1 board +Nucleo_64.menu.pnum.NUCLEO_WL33CC1=Nucleo WL33CC1 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.node="NOD_WL33CC" +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.maximum_size=262144 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.maximum_data_size=32768 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.mcu=cortex-m0plus +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.board=NUCLEO_WL33CC1 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.series=STM32WL3x +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.product_line=STM32WL3xx +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.variant_h=variant_NUCLEO_WL33CCx.h +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.openocd.target=stm32wl3x +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.address=0x10040000 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.mode=hwRstPulse +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.start=0x10000000 +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.parity=none + +# NUCLEO_WL3CC2 board +Nucleo_64.menu.pnum.NUCLEO_WL33CC2=Nucleo WL33CC2 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.node="NOD_WL33CC" +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.maximum_size=262144 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.maximum_data_size=32768 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.mcu=cortex-m0plus +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.board=NUCLEO_WL33CC2 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.series=STM32WL3x +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.product_line=STM32WL3xx +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.variant_h=variant_NUCLEO_WL33CCx.h +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.openocd.target=stm32wl3x +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.address=0x10040000 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.mode=hwRstPulse +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.start=0x10000000 +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.parity=none + # NUCLEO_WL55JC1 board Nucleo_64.menu.pnum.NUCLEO_WL55JC1=Nucleo WL55JC1 Nucleo_64.menu.pnum.NUCLEO_WL55JC1.node="NOD_WL55JC" @@ -1010,17 +1082,17 @@ Nucleo_64.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Nucleo_64.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Nucleo_64.menu.upload_method.jlinkMethod.upload.protocol=jlink -Nucleo_64.menu.upload_method.jlinkMethod.upload.options= +Nucleo_64.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Nucleo_64.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Nucleo_64.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Nucleo_64.menu.upload_method.serialMethod.upload.protocol=serial -Nucleo_64.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +Nucleo_64.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} Nucleo_64.menu.upload_method.serialMethod.upload.tool=stm32CubeProg Nucleo_64.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Nucleo_64.menu.upload_method.dfuMethod.upload.protocol=dfu -Nucleo_64.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Nucleo_64.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Nucleo_64.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Nucleo_64.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -1185,22 +1257,22 @@ Nucleo_32.menu.upload_method.MassStorage.upload.tool=massStorageCopy Nucleo_32.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Nucleo_32.menu.upload_method.swdMethod.upload.protocol=swd -Nucleo_32.menu.upload_method.swdMethod.upload.options= +Nucleo_32.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Nucleo_32.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Nucleo_32.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Nucleo_32.menu.upload_method.jlinkMethod.upload.protocol=jlink -Nucleo_32.menu.upload_method.jlinkMethod.upload.options= +Nucleo_32.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Nucleo_32.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Nucleo_32.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Nucleo_32.menu.upload_method.serialMethod.upload.protocol=serial -Nucleo_32.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +Nucleo_32.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} Nucleo_32.menu.upload_method.serialMethod.upload.tool=stm32CubeProg Nucleo_32.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Nucleo_32.menu.upload_method.dfuMethod.upload.protocol=dfu -Nucleo_32.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Nucleo_32.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Nucleo_32.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Nucleo_32.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -1421,6 +1493,20 @@ Disco.menu.pnum.DISCO_F407VG.build.variant=STM32F4xx/F407V(E-G)T_F417V(E-G)T Disco.menu.pnum.DISCO_F407VG.openocd.target=stm32f4x Disco.menu.pnum.DISCO_F407VG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F407.svd +# DISCO_F411VE board +Disco.menu.pnum.DISCO_F411VE=STM32F411E-DISCO +Disco.menu.pnum.DISCO_F411VE.upload.maximum_size=524288 +Disco.menu.pnum.DISCO_F411VE.upload.maximum_data_size=131072 +Disco.menu.pnum.DISCO_F411VE.build.mcu=cortex-m4 +Disco.menu.pnum.DISCO_F411VE.build.fpu=-mfpu=fpv4-sp-d16 +Disco.menu.pnum.DISCO_F411VE.build.float-abi=-mfloat-abi=hard +Disco.menu.pnum.DISCO_F411VE.build.board=DISCO_F411VE +Disco.menu.pnum.DISCO_F411VE.build.series=STM32F4xx +Disco.menu.pnum.DISCO_F411VE.build.product_line=STM32F411xE +Disco.menu.pnum.DISCO_F411VE.build.variant=STM32F4xx/F411V(C-E)T +Disco.menu.pnum.DISCO_F411VE.openocd.target=stm32f4x +Disco.menu.pnum.DISCO_F411VE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd + # DISCO_F413ZH board Disco.menu.pnum.DISCO_F413ZH=STM32F413H-DISCO Disco.menu.pnum.DISCO_F413ZH.node=DIS_F413ZH @@ -1437,6 +1523,22 @@ Disco.menu.pnum.DISCO_F413ZH.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Disco.menu.pnum.DISCO_F413ZH.openocd.target=stm32f4x Disco.menu.pnum.DISCO_F413ZH.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F413.svd +# DISCO_F429ZI board +Disco.menu.pnum.DISCO_F429ZI= STM32F429ZI-DISCO +Disco.menu.pnum.DISCO_F429ZI.node=DIS_F429ZI +Disco.menu.pnum.DISCO_F429ZI.upload.maximum_size=2097152 +Disco.menu.pnum.DISCO_F429ZI.upload.maximum_data_size=196608 +Disco.menu.pnum.DISCO_F429ZI.build.mcu=cortex-m4 +Disco.menu.pnum.DISCO_F429ZI.build.fpu=-mfpu=fpv4-sp-d16 +Disco.menu.pnum.DISCO_F429ZI.build.float-abi=-mfloat-abi=hard +Disco.menu.pnum.DISCO_F429ZI.build.board=DISCO_F429ZI +Disco.menu.pnum.DISCO_F429ZI.build.series=STM32F4xx +Disco.menu.pnum.DISCO_F429ZI.build.product_line=STM32F429xx +Disco.menu.pnum.DISCO_F429ZI.build.variant=STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y) +Disco.menu.pnum.DISCO_F429ZI.build.variant_h=variant_DISCO_F429ZI.h +Disco.menu.pnum.DISCO_F429ZI.openocd.target=stm32f4x +Disco.menu.pnum.DISCO_F429ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F429.svd + # DISCO_F746NG board Disco.menu.pnum.DISCO_F746NG=STM32F746G-DISCOVERY Disco.menu.pnum.DISCO_F746NG.node=DIS_F746NG @@ -1539,22 +1641,22 @@ Disco.menu.upload_method.MassStorage.upload.tool=massStorageCopy Disco.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Disco.menu.upload_method.swdMethod.upload.protocol=swd -Disco.menu.upload_method.swdMethod.upload.options= +Disco.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Disco.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Disco.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Disco.menu.upload_method.jlinkMethod.upload.protocol=jlink -Disco.menu.upload_method.jlinkMethod.upload.options= +Disco.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Disco.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Disco.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Disco.menu.upload_method.serialMethod.upload.protocol=serial -Disco.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +Disco.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} Disco.menu.upload_method.serialMethod.upload.tool=stm32CubeProg Disco.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Disco.menu.upload_method.dfuMethod.upload.protocol=dfu -Disco.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Disco.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Disco.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Disco.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -1632,17 +1734,17 @@ Eval.menu.pnum.STEVAL_MKBOXPRO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd # Upload menu Eval.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Eval.menu.upload_method.swdMethod.upload.protocol=swd -Eval.menu.upload_method.swdMethod.upload.options= +Eval.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Eval.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Eval.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Eval.menu.upload_method.jlinkMethod.upload.protocol=jlink -Eval.menu.upload_method.jlinkMethod.upload.options= +Eval.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Eval.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Eval.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Eval.menu.upload_method.dfuMethod.upload.protocol=dfu -Eval.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Eval.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Eval.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Eval.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -1829,6 +1931,42 @@ GenC0.menu.pnum.GENERIC_C031F6PX.build.product_line=STM32C031xx GenC0.menu.pnum.GENERIC_C031F6PX.build.variant=STM32C0xx/C031F(4-6)P GenC0.menu.pnum.GENERIC_C031F6PX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd +# Generic C051C6Tx +GenC0.menu.pnum.GENERIC_C051C6TX=Generic C051C6Tx +GenC0.menu.pnum.GENERIC_C051C6TX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051C6TX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C6TX.build.board=GENERIC_C051C6TX +GenC0.menu.pnum.GENERIC_C051C6TX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C6TX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051C6Ux +GenC0.menu.pnum.GENERIC_C051C6UX=Generic C051C6Ux +GenC0.menu.pnum.GENERIC_C051C6UX.upload.maximum_size=32768 +GenC0.menu.pnum.GENERIC_C051C6UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C6UX.build.board=GENERIC_C051C6UX +GenC0.menu.pnum.GENERIC_C051C6UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C6UX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C6UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051C8Tx +GenC0.menu.pnum.GENERIC_C051C8TX=Generic C051C8Tx +GenC0.menu.pnum.GENERIC_C051C8TX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051C8TX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C8TX.build.board=GENERIC_C051C8TX +GenC0.menu.pnum.GENERIC_C051C8TX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C8TX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + +# Generic C051C8Ux +GenC0.menu.pnum.GENERIC_C051C8UX=Generic C051C8Ux +GenC0.menu.pnum.GENERIC_C051C8UX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C051C8UX.upload.maximum_data_size=12288 +GenC0.menu.pnum.GENERIC_C051C8UX.build.board=GENERIC_C051C8UX +GenC0.menu.pnum.GENERIC_C051C8UX.build.product_line=STM32C051xx +GenC0.menu.pnum.GENERIC_C051C8UX.build.variant=STM32C0xx/C051C(6-8)(T-U) +GenC0.menu.pnum.GENERIC_C051C8UX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C051.svd + # Generic C071G8Ux GenC0.menu.pnum.GENERIC_C071G8UX=Generic C071G8Ux GenC0.menu.pnum.GENERIC_C071G8UX.upload.maximum_size=65536 @@ -1871,16 +2009,43 @@ GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_size=131072 GenC0.menu.pnum.GENERIC_C092CBTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092CBTX.build.board=GENERIC_C092CBTX GenC0.menu.pnum.GENERIC_C092CBTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092CBTX.build.variant=STM32C0xx/C092C(B-C)(T-U) GenC0.menu.pnum.GENERIC_C092CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd +# Generic C092CBUx +GenC0.menu.pnum.GENERIC_C092CBUX=Generic C092CBUx +GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C092CBUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CBUX.build.board=GENERIC_C092CBUX +GenC0.menu.pnum.GENERIC_C092CBUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CBUX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092CCTx +GenC0.menu.pnum.GENERIC_C092CCTX=Generic C092CCTx +GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092CCTX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CCTX.build.board=GENERIC_C092CCTX +GenC0.menu.pnum.GENERIC_C092CCTX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CCTX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + +# Generic C092CCUx +GenC0.menu.pnum.GENERIC_C092CCUX=Generic C092CCUx +GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_size=262144 +GenC0.menu.pnum.GENERIC_C092CCUX.upload.maximum_data_size=30720 +GenC0.menu.pnum.GENERIC_C092CCUX.build.board=GENERIC_C092CCUX +GenC0.menu.pnum.GENERIC_C092CCUX.build.product_line=STM32C092xx +GenC0.menu.pnum.GENERIC_C092CCUX.build.variant=STM32C0xx/C092C(B-C)(T-U) +GenC0.menu.pnum.GENERIC_C092CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd + # Generic C092RBTx GenC0.menu.pnum.GENERIC_C092RBTX=Generic C092RBTx GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_size=131072 GenC0.menu.pnum.GENERIC_C092RBTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RBTX.build.board=GENERIC_C092RBTX GenC0.menu.pnum.GENERIC_C092RBTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RBTX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092RCIx @@ -1889,7 +2054,7 @@ GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092RCIX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RCIX.build.board=GENERIC_C092RCIX GenC0.menu.pnum.GENERIC_C092RCIX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCIX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Generic C092RCTx @@ -1898,28 +2063,28 @@ GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_size=262144 GenC0.menu.pnum.GENERIC_C092RCTX.upload.maximum_data_size=30720 GenC0.menu.pnum.GENERIC_C092RCTX.build.board=GENERIC_C092RCTX GenC0.menu.pnum.GENERIC_C092RCTX.build.product_line=STM32C092xx -GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092CBT_C092RBT_C092RC(I-T) +GenC0.menu.pnum.GENERIC_C092RCTX.build.variant=STM32C0xx/C092RBT_C092RC(I-T) GenC0.menu.pnum.GENERIC_C092RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C092.svd # Upload menu GenC0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenC0.menu.upload_method.swdMethod.upload.protocol=swd -GenC0.menu.upload_method.swdMethod.upload.options= +GenC0.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenC0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenC0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenC0.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenC0.menu.upload_method.jlinkMethod.upload.options= +GenC0.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenC0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenC0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenC0.menu.upload_method.serialMethod.upload.protocol=serial -GenC0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenC0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenC0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenC0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenC0.menu.upload_method.dfuMethod.upload.protocol=dfu -GenC0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenC0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenC0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenC0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -2847,22 +3012,22 @@ GenF0.menu.pnum.GENERIC_F098VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenF0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenF0.menu.upload_method.swdMethod.upload.protocol=swd -GenF0.menu.upload_method.swdMethod.upload.options= +GenF0.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenF0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenF0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenF0.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenF0.menu.upload_method.jlinkMethod.upload.options= +GenF0.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenF0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenF0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF0.menu.upload_method.serialMethod.upload.protocol=serial -GenF0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenF0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenF0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenF0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenF0.menu.upload_method.dfuMethod.upload.protocol=dfu -GenF0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenF0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenF0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenF0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -2944,6 +3109,16 @@ GenF1.menu.pnum.BLACKPILL_F103CB.build.variant_h=variant_PILL_F103Cx.h GenF1.menu.pnum.BLACKPILL_F103CB.build.variant=STM32F1xx/F103C8T_F103CB(T-U) GenF1.menu.pnum.BLACKPILL_F103CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd +# Databoard board +GenF1.menu.pnum.DATABOARD=Databoard +GenF1.menu.pnum.DATABOARD.upload.maximum_size=65536 +GenF1.menu.pnum.DATABOARD.upload.maximum_data_size=20480 +GenF1.menu.pnum.DATABOARD.build.board=DATABOARD +GenF1.menu.pnum.DATABOARD.build.product_line=STM32F103xB +GenF1.menu.pnum.DATABOARD.build.variant_h=variant_{build.board}.h +GenF1.menu.pnum.DATABOARD.build.variant=STM32F1xx/F103C8T_F103CB(T-U) +GenF1.menu.pnum.DATABOARD.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd + # VCCGND_F103ZET6_MINI board GenF1.menu.pnum.VCCGND_F103ZET6_MINI=VCCGND F103ZET6 Mini GenF1.menu.pnum.VCCGND_F103ZET6_MINI.upload.maximum_size=524288 @@ -3684,22 +3859,22 @@ GenF1.menu.pnum.GENERIC_F103ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenF1.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenF1.menu.upload_method.swdMethod.upload.protocol=swd -GenF1.menu.upload_method.swdMethod.upload.options= +GenF1.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenF1.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenF1.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenF1.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenF1.menu.upload_method.jlinkMethod.upload.options= +GenF1.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenF1.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenF1.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF1.menu.upload_method.serialMethod.upload.protocol=serial -GenF1.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenF1.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenF1.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenF1.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenF1.menu.upload_method.dfuMethod.upload.protocol=dfu -GenF1.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenF1.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenF1.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenF1.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -4176,22 +4351,22 @@ GenF2.menu.pnum.GENERIC_F217ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenF2.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenF2.menu.upload_method.swdMethod.upload.protocol=swd -GenF2.menu.upload_method.swdMethod.upload.options= +GenF2.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenF2.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenF2.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenF2.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenF2.menu.upload_method.jlinkMethod.upload.options= +GenF2.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenF2.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenF2.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF2.menu.upload_method.serialMethod.upload.protocol=serial -GenF2.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenF2.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenF2.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenF2.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenF2.menu.upload_method.dfuMethod.upload.protocol=dfu -GenF2.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenF2.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenF2.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenF2.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -4644,22 +4819,22 @@ GenF3.menu.pnum.GENERIC_F398VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenF3.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenF3.menu.upload_method.swdMethod.upload.protocol=swd -GenF3.menu.upload_method.swdMethod.upload.options= +GenF3.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenF3.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenF3.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenF3.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenF3.menu.upload_method.jlinkMethod.upload.options= +GenF3.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenF3.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenF3.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF3.menu.upload_method.serialMethod.upload.protocol=serial -GenF3.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenF3.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenF3.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenF3.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenF3.menu.upload_method.dfuMethod.upload.protocol=dfu -GenF3.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenF3.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenF3.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenF3.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -5231,6 +5406,24 @@ GenF4.menu.pnum.GENERIC_F411RETX.build.product_line=STM32F411xE GenF4.menu.pnum.GENERIC_F411RETX.build.variant=STM32F4xx/F411R(C-E)T GenF4.menu.pnum.GENERIC_F411RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd +# Generic F411VCTx +GenF4.menu.pnum.GENERIC_F411VCTX=Generic F411VCTx +GenF4.menu.pnum.GENERIC_F411VCTX.upload.maximum_size=262144 +GenF4.menu.pnum.GENERIC_F411VCTX.upload.maximum_data_size=131072 +GenF4.menu.pnum.GENERIC_F411VCTX.build.board=GENERIC_F411VCTX +GenF4.menu.pnum.GENERIC_F411VCTX.build.product_line=STM32F411xE +GenF4.menu.pnum.GENERIC_F411VCTX.build.variant=STM32F4xx/F411V(C-E)T +GenF4.menu.pnum.GENERIC_F411VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd + +# Generic F411VETx +GenF4.menu.pnum.GENERIC_F411VETX=Generic F411VETx +GenF4.menu.pnum.GENERIC_F411VETX.upload.maximum_size=524288 +GenF4.menu.pnum.GENERIC_F411VETX.upload.maximum_data_size=131072 +GenF4.menu.pnum.GENERIC_F411VETX.build.board=GENERIC_F411VETX +GenF4.menu.pnum.GENERIC_F411VETX.build.product_line=STM32F411xE +GenF4.menu.pnum.GENERIC_F411VETX.build.variant=STM32F4xx/F411V(C-E)T +GenF4.menu.pnum.GENERIC_F411VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd + # Generic F412CEUx GenF4.menu.pnum.GENERIC_F412CEUX=Generic F412CEUx GenF4.menu.pnum.GENERIC_F412CEUX.upload.maximum_size=524288 @@ -5738,22 +5931,22 @@ GenF4.menu.pnum.GENERIC_F446ZETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenF4.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenF4.menu.upload_method.swdMethod.upload.protocol=swd -GenF4.menu.upload_method.swdMethod.upload.options= +GenF4.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenF4.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenF4.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenF4.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenF4.menu.upload_method.jlinkMethod.upload.options= +GenF4.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenF4.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenF4.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF4.menu.upload_method.serialMethod.upload.protocol=serial -GenF4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenF4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenF4.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenF4.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenF4.menu.upload_method.dfuMethod.upload.protocol=dfu -GenF4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenF4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenF4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenF4.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -6291,22 +6484,22 @@ GenF7.menu.pnum.GENERIC_F777ZITX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenF7.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenF7.menu.upload_method.swdMethod.upload.protocol=swd -GenF7.menu.upload_method.swdMethod.upload.options= +GenF7.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenF7.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenF7.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenF7.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenF7.menu.upload_method.jlinkMethod.upload.options= +GenF7.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenF7.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenF7.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF7.menu.upload_method.serialMethod.upload.protocol=serial -GenF7.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenF7.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenF7.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenF7.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenF7.menu.upload_method.dfuMethod.upload.protocol=dfu -GenF7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenF7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenF7.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenF7.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -7719,22 +7912,22 @@ GenG0.menu.pnum.GENERIC_G0C1RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenG0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenG0.menu.upload_method.swdMethod.upload.protocol=swd -GenG0.menu.upload_method.swdMethod.upload.options= +GenG0.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenG0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenG0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenG0.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenG0.menu.upload_method.jlinkMethod.upload.options= +GenG0.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenG0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenG0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenG0.menu.upload_method.serialMethod.upload.protocol=serial -GenG0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenG0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenG0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenG0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenG0.menu.upload_method.dfuMethod.upload.protocol=dfu -GenG0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenG0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenG0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenG0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -8797,7 +8990,7 @@ GenG4.menu.pnum.GENERIC_G484VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491CCTx GenG4.menu.pnum.GENERIC_G491CCTX=Generic G491CCTx GenG4.menu.pnum.GENERIC_G491CCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491CCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491CCTX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491CCTX.build.board=GENERIC_G491CCTX GenG4.menu.pnum.GENERIC_G491CCTX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491CCTX.build.variant=STM32G4xx/G491C(C-E)T_G4A1CET @@ -8806,7 +8999,7 @@ GenG4.menu.pnum.GENERIC_G491CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491CETx GenG4.menu.pnum.GENERIC_G491CETX=Generic G491CETx GenG4.menu.pnum.GENERIC_G491CETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491CETX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491CETX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491CETX.build.board=GENERIC_G491CETX GenG4.menu.pnum.GENERIC_G491CETX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491CETX.build.variant=STM32G4xx/G491C(C-E)T_G4A1CET @@ -8815,7 +9008,7 @@ GenG4.menu.pnum.GENERIC_G491CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491KCUx GenG4.menu.pnum.GENERIC_G491KCUX=Generic G491KCUx GenG4.menu.pnum.GENERIC_G491KCUX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491KCUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491KCUX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491KCUX.build.board=GENERIC_G491KCUX GenG4.menu.pnum.GENERIC_G491KCUX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491KCUX.build.variant=STM32G4xx/G491K(C-E)U_G4A1KEU @@ -8824,7 +9017,7 @@ GenG4.menu.pnum.GENERIC_G491KCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491KEUx GenG4.menu.pnum.GENERIC_G491KEUX=Generic G491KEUx GenG4.menu.pnum.GENERIC_G491KEUX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491KEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491KEUX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491KEUX.build.board=GENERIC_G491KEUX GenG4.menu.pnum.GENERIC_G491KEUX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491KEUX.build.variant=STM32G4xx/G491K(C-E)U_G4A1KEU @@ -8833,7 +9026,7 @@ GenG4.menu.pnum.GENERIC_G491KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491MCSx GenG4.menu.pnum.GENERIC_G491MCSX=Generic G491MCSx GenG4.menu.pnum.GENERIC_G491MCSX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491MCSX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491MCSX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491MCSX.build.board=GENERIC_G491MCSX GenG4.menu.pnum.GENERIC_G491MCSX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491MCSX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T) @@ -8842,7 +9035,7 @@ GenG4.menu.pnum.GENERIC_G491MCSX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491MESx GenG4.menu.pnum.GENERIC_G491MESX=Generic G491MESx GenG4.menu.pnum.GENERIC_G491MESX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491MESX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491MESX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491MESX.build.board=GENERIC_G491MESX GenG4.menu.pnum.GENERIC_G491MESX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491MESX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T) @@ -8851,7 +9044,7 @@ GenG4.menu.pnum.GENERIC_G491MESX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491MCTx GenG4.menu.pnum.GENERIC_G491MCTX=Generic G491MCTx GenG4.menu.pnum.GENERIC_G491MCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491MCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491MCTX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491MCTX.build.board=GENERIC_G491MCTX GenG4.menu.pnum.GENERIC_G491MCTX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491MCTX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T) @@ -8860,7 +9053,7 @@ GenG4.menu.pnum.GENERIC_G491MCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491METx GenG4.menu.pnum.GENERIC_G491METX=Generic G491METx GenG4.menu.pnum.GENERIC_G491METX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491METX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491METX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491METX.build.board=GENERIC_G491METX GenG4.menu.pnum.GENERIC_G491METX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491METX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T) @@ -8869,7 +9062,7 @@ GenG4.menu.pnum.GENERIC_G491METX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491RCIx GenG4.menu.pnum.GENERIC_G491RCIX=Generic G491RCIx GenG4.menu.pnum.GENERIC_G491RCIX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491RCIX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491RCIX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491RCIX.build.board=GENERIC_G491RCIX GenG4.menu.pnum.GENERIC_G491RCIX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491RCIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8878,7 +9071,7 @@ GenG4.menu.pnum.GENERIC_G491RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491REIx GenG4.menu.pnum.GENERIC_G491REIX=Generic G491REIx GenG4.menu.pnum.GENERIC_G491REIX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491REIX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491REIX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491REIX.build.board=GENERIC_G491REIX GenG4.menu.pnum.GENERIC_G491REIX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8887,7 +9080,7 @@ GenG4.menu.pnum.GENERIC_G491REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491RCTx GenG4.menu.pnum.GENERIC_G491RCTX=Generic G491RCTx GenG4.menu.pnum.GENERIC_G491RCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491RCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491RCTX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491RCTX.build.board=GENERIC_G491RCTX GenG4.menu.pnum.GENERIC_G491RCTX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491RCTX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8896,7 +9089,7 @@ GenG4.menu.pnum.GENERIC_G491RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491RETx GenG4.menu.pnum.GENERIC_G491RETX=Generic G491RETx GenG4.menu.pnum.GENERIC_G491RETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491RETX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491RETX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491RETX.build.board=GENERIC_G491RETX GenG4.menu.pnum.GENERIC_G491RETX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491RETX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8905,7 +9098,7 @@ GenG4.menu.pnum.GENERIC_G491RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491RETxZ GenG4.menu.pnum.GENERIC_G491RETXZ=Generic G491RETxZ GenG4.menu.pnum.GENERIC_G491RETXZ.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491RETXZ.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491RETXZ.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491RETXZ.build.board=GENERIC_G491RETXZ GenG4.menu.pnum.GENERIC_G491RETXZ.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491RETXZ.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8913,7 +9106,7 @@ GenG4.menu.pnum.GENERIC_G491RETXZ.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T # Generic G491REYx GenG4.menu.pnum.GENERIC_G491REYX=Generic G491REYx GenG4.menu.pnum.GENERIC_G491REYX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491REYX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491REYX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491REYX.build.board=GENERIC_G491REYX GenG4.menu.pnum.GENERIC_G491REYX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8922,7 +9115,7 @@ GenG4.menu.pnum.GENERIC_G491REYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491VCTx GenG4.menu.pnum.GENERIC_G491VCTX=Generic G491VCTx GenG4.menu.pnum.GENERIC_G491VCTX.upload.maximum_size=262144 -GenG4.menu.pnum.GENERIC_G491VCTX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491VCTX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491VCTX.build.board=GENERIC_G491VCTX GenG4.menu.pnum.GENERIC_G491VCTX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491VCTX.build.variant=STM32G4xx/G491V(C-E)T_G4A1VET @@ -8931,7 +9124,7 @@ GenG4.menu.pnum.GENERIC_G491VCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G491VETx GenG4.menu.pnum.GENERIC_G491VETX=Generic G491VETx GenG4.menu.pnum.GENERIC_G491VETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G491VETX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491VETX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G491VETX.build.board=GENERIC_G491VETX GenG4.menu.pnum.GENERIC_G491VETX.build.product_line=STM32G491xx GenG4.menu.pnum.GENERIC_G491VETX.build.variant=STM32G4xx/G491V(C-E)T_G4A1VET @@ -8940,7 +9133,7 @@ GenG4.menu.pnum.GENERIC_G491VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1REIx GenG4.menu.pnum.GENERIC_G4A1REIX=Generic G4A1REIx GenG4.menu.pnum.GENERIC_G4A1REIX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1REIX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1REIX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1REIX.build.board=GENERIC_G4A1REIX GenG4.menu.pnum.GENERIC_G4A1REIX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8949,7 +9142,7 @@ GenG4.menu.pnum.GENERIC_G4A1REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1CETx GenG4.menu.pnum.GENERIC_G4A1CETX=Generic G4A1CETx GenG4.menu.pnum.GENERIC_G4A1CETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1CETX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1CETX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1CETX.build.board=GENERIC_G4A1CETX GenG4.menu.pnum.GENERIC_G4A1CETX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1CETX.build.variant=STM32G4xx/G491C(C-E)T_G4A1CET @@ -8958,7 +9151,7 @@ GenG4.menu.pnum.GENERIC_G4A1CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1KEUx GenG4.menu.pnum.GENERIC_G4A1KEUX=Generic G4A1KEUx GenG4.menu.pnum.GENERIC_G4A1KEUX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1KEUX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1KEUX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1KEUX.build.board=GENERIC_G4A1KEUX GenG4.menu.pnum.GENERIC_G4A1KEUX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1KEUX.build.variant=STM32G4xx/G491K(C-E)U_G4A1KEU @@ -8967,7 +9160,7 @@ GenG4.menu.pnum.GENERIC_G4A1KEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1MESx GenG4.menu.pnum.GENERIC_G4A1MESX=Generic G4A1MESx GenG4.menu.pnum.GENERIC_G4A1MESX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1MESX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1MESX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1MESX.build.board=GENERIC_G4A1MESX GenG4.menu.pnum.GENERIC_G4A1MESX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1MESX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T) @@ -8976,7 +9169,7 @@ GenG4.menu.pnum.GENERIC_G4A1MESX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1METx GenG4.menu.pnum.GENERIC_G4A1METX=Generic G4A1METx GenG4.menu.pnum.GENERIC_G4A1METX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1METX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1METX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1METX.build.board=GENERIC_G4A1METX GenG4.menu.pnum.GENERIC_G4A1METX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1METX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T) @@ -8985,7 +9178,7 @@ GenG4.menu.pnum.GENERIC_G4A1METX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1RETx GenG4.menu.pnum.GENERIC_G4A1RETX=Generic G4A1RETx GenG4.menu.pnum.GENERIC_G4A1RETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1RETX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1RETX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1RETX.build.board=GENERIC_G4A1RETX GenG4.menu.pnum.GENERIC_G4A1RETX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1RETX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -8994,7 +9187,7 @@ GenG4.menu.pnum.GENERIC_G4A1RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1REYx GenG4.menu.pnum.GENERIC_G4A1REYX=Generic G4A1REYx GenG4.menu.pnum.GENERIC_G4A1REYX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1REYX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1REYX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1REYX.build.board=GENERIC_G4A1REYX GenG4.menu.pnum.GENERIC_G4A1REYX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) @@ -9003,7 +9196,7 @@ GenG4.menu.pnum.GENERIC_G4A1REYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic G4A1VETx GenG4.menu.pnum.GENERIC_G4A1VETX=Generic G4A1VETx GenG4.menu.pnum.GENERIC_G4A1VETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G4A1VETX.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G4A1VETX.upload.maximum_data_size=114688 GenG4.menu.pnum.GENERIC_G4A1VETX.build.board=GENERIC_G4A1VETX GenG4.menu.pnum.GENERIC_G4A1VETX.build.product_line=STM32G4A1xx GenG4.menu.pnum.GENERIC_G4A1VETX.build.variant=STM32G4xx/G491V(C-E)T_G4A1VET @@ -9012,22 +9205,22 @@ GenG4.menu.pnum.GENERIC_G4A1VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenG4.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenG4.menu.upload_method.swdMethod.upload.protocol=swd -GenG4.menu.upload_method.swdMethod.upload.options= +GenG4.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenG4.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenG4.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenG4.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenG4.menu.upload_method.jlinkMethod.upload.options= +GenG4.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenG4.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenG4.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenG4.menu.upload_method.serialMethod.upload.protocol=serial -GenG4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenG4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenG4.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenG4.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenG4.menu.upload_method.dfuMethod.upload.protocol=dfu -GenG4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenG4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenG4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenG4.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -9201,22 +9394,22 @@ GenH5.menu.pnum.GENERIC_H573ZITX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenH5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenH5.menu.upload_method.swdMethod.upload.protocol=swd -GenH5.menu.upload_method.swdMethod.upload.options= +GenH5.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenH5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenH5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenH5.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenH5.menu.upload_method.jlinkMethod.upload.options= +GenH5.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenH5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenH5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenH5.menu.upload_method.serialMethod.upload.protocol=serial -GenH5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenH5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenH5.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenH5.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenH5.menu.upload_method.dfuMethod.upload.protocol=dfu -GenH5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenH5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenH5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenH5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -9329,6 +9522,42 @@ GenH7.menu.pnum.WeActMiniH750VBTX.build.variant_h=variant_WeActMiniH7xx.h GenH7.menu.pnum.WeActMiniH750VBTX.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS GenH7.menu.pnum.WeActMiniH750VBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H750.svd +# Generic H723VEHx +GenH7.menu.pnum.GENERIC_H723VEHX=Generic H723VEHx +GenH7.menu.pnum.GENERIC_H723VEHX.upload.maximum_size=524288 +GenH7.menu.pnum.GENERIC_H723VEHX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H723VEHX.build.board=GENERIC_H723VEHX +GenH7.menu.pnum.GENERIC_H723VEHX.build.product_line=STM32H723xx +GenH7.menu.pnum.GENERIC_H723VEHX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H723VEHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H723.svd + +# Generic H723VETx +GenH7.menu.pnum.GENERIC_H723VETX=Generic H723VETx +GenH7.menu.pnum.GENERIC_H723VETX.upload.maximum_size=524288 +GenH7.menu.pnum.GENERIC_H723VETX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H723VETX.build.board=GENERIC_H723VETX +GenH7.menu.pnum.GENERIC_H723VETX.build.product_line=STM32H723xx +GenH7.menu.pnum.GENERIC_H723VETX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H723VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H723.svd + +# Generic H723VGHx +GenH7.menu.pnum.GENERIC_H723VGHX=Generic H723VGHx +GenH7.menu.pnum.GENERIC_H723VGHX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H723VGHX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H723VGHX.build.board=GENERIC_H723VGHX +GenH7.menu.pnum.GENERIC_H723VGHX.build.product_line=STM32H723xx +GenH7.menu.pnum.GENERIC_H723VGHX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H723VGHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H723.svd + +# Generic H723VGTx +GenH7.menu.pnum.GENERIC_H723VGTX=Generic H723VGTx +GenH7.menu.pnum.GENERIC_H723VGTX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H723VGTX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H723VGTX.build.board=GENERIC_H723VGTX +GenH7.menu.pnum.GENERIC_H723VGTX.build.product_line=STM32H723xx +GenH7.menu.pnum.GENERIC_H723VGTX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H723VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H723.svd + # Generic H723ZETx GenH7.menu.pnum.GENERIC_H723ZETX=Generic H723ZETx GenH7.menu.pnum.GENERIC_H723ZETX.upload.maximum_size=524288 @@ -9347,6 +9576,24 @@ GenH7.menu.pnum.GENERIC_H723ZGTX.build.product_line=STM32H723xx GenH7.menu.pnum.GENERIC_H723ZGTX.build.variant=STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT GenH7.menu.pnum.GENERIC_H723ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H723.svd +# Generic H730VBHx +GenH7.menu.pnum.GENERIC_H730VBHX=Generic H730VBHx +GenH7.menu.pnum.GENERIC_H730VBHX.upload.maximum_size=131072 +GenH7.menu.pnum.GENERIC_H730VBHX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H730VBHX.build.board=GENERIC_H730VBHX +GenH7.menu.pnum.GENERIC_H730VBHX.build.product_line=STM32H730xx +GenH7.menu.pnum.GENERIC_H730VBHX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H730VBHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H730.svd + +# Generic H730VBTx +GenH7.menu.pnum.GENERIC_H730VBTX=Generic H730VBTx +GenH7.menu.pnum.GENERIC_H730VBTX.upload.maximum_size=131072 +GenH7.menu.pnum.GENERIC_H730VBTX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H730VBTX.build.board=GENERIC_H730VBTX +GenH7.menu.pnum.GENERIC_H730VBTX.build.product_line=STM32H730xx +GenH7.menu.pnum.GENERIC_H730VBTX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H730VBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H730.svd + # Generic H730ZBTx GenH7.menu.pnum.GENERIC_H730ZBTX=Generic H730ZBTx GenH7.menu.pnum.GENERIC_H730ZBTX.upload.maximum_size=131072 @@ -9356,6 +9603,24 @@ GenH7.menu.pnum.GENERIC_H730ZBTX.build.product_line=STM32H730xx GenH7.menu.pnum.GENERIC_H730ZBTX.build.variant=STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT GenH7.menu.pnum.GENERIC_H730ZBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H730.svd +# Generic H733VGHx +GenH7.menu.pnum.GENERIC_H733VGHX=Generic H733VGHx +GenH7.menu.pnum.GENERIC_H733VGHX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H733VGHX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H733VGHX.build.board=GENERIC_H733VGHX +GenH7.menu.pnum.GENERIC_H733VGHX.build.product_line=STM32H733xx +GenH7.menu.pnum.GENERIC_H733VGHX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H733VGHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H733.svd + +# Generic H733VGTx +GenH7.menu.pnum.GENERIC_H733VGTX=Generic H733VGTx +GenH7.menu.pnum.GENERIC_H733VGTX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H733VGTX.upload.maximum_data_size=528384 +GenH7.menu.pnum.GENERIC_H733VGTX.build.board=GENERIC_H733VGTX +GenH7.menu.pnum.GENERIC_H733VGTX.build.product_line=STM32H733xx +GenH7.menu.pnum.GENERIC_H733VGTX.build.variant=STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T) +GenH7.menu.pnum.GENERIC_H733VGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H733.svd + # Generic H733ZGTx GenH7.menu.pnum.GENERIC_H733ZGTX=Generic H733ZGTx GenH7.menu.pnum.GENERIC_H733ZGTX.upload.maximum_size=1048576 @@ -9599,6 +9864,24 @@ GenH7.menu.pnum.GENERIC_H745XIHX.build.product_line=STM32H745xx GenH7.menu.pnum.GENERIC_H745XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH GenH7.menu.pnum.GENERIC_H745XIHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd +# Generic H745ZGTx +GenH7.menu.pnum.GENERIC_H745ZGTX=Generic H745ZGTx +GenH7.menu.pnum.GENERIC_H745ZGTX.upload.maximum_size=1048576 +GenH7.menu.pnum.GENERIC_H745ZGTX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H745ZGTX.build.board=GENERIC_H745ZGTX +GenH7.menu.pnum.GENERIC_H745ZGTX.build.product_line=STM32H745xG +GenH7.menu.pnum.GENERIC_H745ZGTX.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT +GenH7.menu.pnum.GENERIC_H745ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd + +# Generic H745ZITx +GenH7.menu.pnum.GENERIC_H745ZITX=Generic H745ZITx +GenH7.menu.pnum.GENERIC_H745ZITX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H745ZITX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H745ZITX.build.board=GENERIC_H745ZITX +GenH7.menu.pnum.GENERIC_H745ZITX.build.product_line=STM32H745xx +GenH7.menu.pnum.GENERIC_H745ZITX.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT +GenH7.menu.pnum.GENERIC_H745ZITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd + # Generic H747AGIx GenH7.menu.pnum.GENERIC_H747AGIX=Generic H747AGIx GenH7.menu.pnum.GENERIC_H747AGIX.upload.maximum_size=1048576 @@ -9761,6 +10044,15 @@ GenH7.menu.pnum.GENERIC_H755XIHX.build.product_line=STM32H755xx GenH7.menu.pnum.GENERIC_H755XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH GenH7.menu.pnum.GENERIC_H755XIHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H755_CM7.svd +# Generic H755ZITx +GenH7.menu.pnum.GENERIC_H755ZITX=Generic H755ZITx +GenH7.menu.pnum.GENERIC_H755ZITX.upload.maximum_size=2097152 +GenH7.menu.pnum.GENERIC_H755ZITX.upload.maximum_data_size=884736 +GenH7.menu.pnum.GENERIC_H755ZITX.build.board=GENERIC_H755ZITX +GenH7.menu.pnum.GENERIC_H755ZITX.build.product_line=STM32H755xx +GenH7.menu.pnum.GENERIC_H755ZITX.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT +GenH7.menu.pnum.GENERIC_H755ZITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H755_CM7.svd + # Generic H757AIIx GenH7.menu.pnum.GENERIC_H757AIIX=Generic H757AIIx GenH7.menu.pnum.GENERIC_H757AIIX.upload.maximum_size=2097152 @@ -9881,22 +10173,22 @@ GenH7.menu.pnum.GENERIC_H7B3ZITXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/ # Upload menu GenH7.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenH7.menu.upload_method.swdMethod.upload.protocol=swd -GenH7.menu.upload_method.swdMethod.upload.options= +GenH7.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenH7.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenH7.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenH7.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenH7.menu.upload_method.jlinkMethod.upload.options= +GenH7.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenH7.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenH7.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenH7.menu.upload_method.serialMethod.upload.protocol=serial -GenH7.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenH7.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenH7.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenH7.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenH7.menu.upload_method.dfuMethod.upload.protocol=dfu -GenH7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenH7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenH7.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenH7.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -11176,22 +11468,22 @@ GenL0.menu.pnum.GENERIC_L083V8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenL0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenL0.menu.upload_method.swdMethod.upload.protocol=swd -GenL0.menu.upload_method.swdMethod.upload.options= +GenL0.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenL0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenL0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenL0.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenL0.menu.upload_method.jlinkMethod.upload.options= +GenL0.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenL0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenL0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL0.menu.upload_method.serialMethod.upload.protocol=serial -GenL0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenL0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenL0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenL0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenL0.menu.upload_method.dfuMethod.upload.protocol=dfu -GenL0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenL0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenL0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenL0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -11513,22 +11805,22 @@ GenL1.menu.pnum.GENERIC_L162ZDTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenL1.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenL1.menu.upload_method.swdMethod.upload.protocol=swd -GenL1.menu.upload_method.swdMethod.upload.options= +GenL1.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenL1.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenL1.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenL1.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenL1.menu.upload_method.jlinkMethod.upload.options= +GenL1.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenL1.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenL1.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL1.menu.upload_method.serialMethod.upload.protocol=serial -GenL1.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenL1.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenL1.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenL1.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenL1.menu.upload_method.dfuMethod.upload.protocol=dfu -GenL1.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenL1.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenL1.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenL1.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -12348,22 +12640,22 @@ GenL4.menu.pnum.GENERIC_L4S9ZIYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenL4.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenL4.menu.upload_method.swdMethod.upload.protocol=swd -GenL4.menu.upload_method.swdMethod.upload.options= +GenL4.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenL4.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenL4.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenL4.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenL4.menu.upload_method.jlinkMethod.upload.options= +GenL4.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenL4.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenL4.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL4.menu.upload_method.serialMethod.upload.protocol=serial -GenL4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenL4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenL4.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenL4.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenL4.menu.upload_method.dfuMethod.upload.protocol=dfu -GenL4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenL4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenL4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenL4.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -12453,22 +12745,22 @@ GenL5.menu.pnum.GENERIC_L562ZETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/ # Upload menu GenL5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenL5.menu.upload_method.swdMethod.upload.protocol=swd -GenL5.menu.upload_method.swdMethod.upload.options= +GenL5.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenL5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenL5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenL5.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenL5.menu.upload_method.jlinkMethod.upload.options= +GenL5.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenL5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenL5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL5.menu.upload_method.serialMethod.upload.protocol=serial -GenL5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenL5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenL5.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenL5.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenL5.menu.upload_method.dfuMethod.upload.protocol=dfu -GenL5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenL5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenL5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenL5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -12646,22 +12938,22 @@ GenU0.menu.pnum.GENERIC_U083RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenU0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenU0.menu.upload_method.swdMethod.upload.protocol=swd -GenU0.menu.upload_method.swdMethod.upload.options= +GenU0.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenU0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenU0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenU0.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenU0.menu.upload_method.jlinkMethod.upload.options= +GenU0.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenU0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenU0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenU0.menu.upload_method.serialMethod.upload.protocol=serial -GenU0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenU0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenU0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenU0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenU0.menu.upload_method.dfuMethod.upload.protocol=dfu -GenU0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenU0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenU0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg #GenU0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) @@ -12697,7 +12989,7 @@ GenU3.menu.pnum.GENERIC_U375RETXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RETXQ.build.board=GENERIC_U375RETXQ GenU3.menu.pnum.GENERIC_U375RETXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RETXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U375RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375RGTxQ GenU3.menu.pnum.GENERIC_U375RGTXQ=Generic U375RGTxQ @@ -12706,7 +12998,7 @@ GenU3.menu.pnum.GENERIC_U375RGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375RGTXQ.build.board=GENERIC_U375RGTXQ GenU3.menu.pnum.GENERIC_U375RGTXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375RGTXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U375RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VEIx GenU3.menu.pnum.GENERIC_U375VEIX=Generic U375VEIx @@ -12715,7 +13007,7 @@ GenU3.menu.pnum.GENERIC_U375VEIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VEIX.build.board=GENERIC_U375VEIX GenU3.menu.pnum.GENERIC_U375VEIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VEIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U375VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VEIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VEIxQ GenU3.menu.pnum.GENERIC_U375VEIXQ=Generic U375VEIxQ @@ -12724,7 +13016,7 @@ GenU3.menu.pnum.GENERIC_U375VEIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VEIXQ.build.board=GENERIC_U375VEIXQ GenU3.menu.pnum.GENERIC_U375VEIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VEIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U375VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGIx GenU3.menu.pnum.GENERIC_U375VGIX=Generic U375VGIx @@ -12733,7 +13025,7 @@ GenU3.menu.pnum.GENERIC_U375VGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGIX.build.board=GENERIC_U375VGIX GenU3.menu.pnum.GENERIC_U375VGIX.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U375VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U375VGIxQ GenU3.menu.pnum.GENERIC_U375VGIXQ=Generic U375VGIxQ @@ -12742,7 +13034,7 @@ GenU3.menu.pnum.GENERIC_U375VGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U375VGIXQ.build.board=GENERIC_U375VGIXQ GenU3.menu.pnum.GENERIC_U375VGIXQ.build.product_line=STM32U375xx GenU3.menu.pnum.GENERIC_U375VGIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U375VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U375VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U375.svd # Generic U385RGTxQ GenU3.menu.pnum.GENERIC_U385RGTXQ=Generic U385RGTxQ @@ -12751,7 +13043,7 @@ GenU3.menu.pnum.GENERIC_U385RGTXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385RGTXQ.build.board=GENERIC_U385RGTXQ GenU3.menu.pnum.GENERIC_U385RGTXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385RGTXQ.build.variant=STM32U3xx/U375R(E-G)TxQ_U385RGTxQ -GenU3.menu.pnum.GENERIC_U385RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385RGTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Generic U385VGIx GenU3.menu.pnum.GENERIC_U385VGIX=Generic U385VGIx @@ -12760,7 +13052,7 @@ GenU3.menu.pnum.GENERIC_U385VGIX.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGIX.build.board=GENERIC_U385VGIX GenU3.menu.pnum.GENERIC_U385VGIX.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGIX.build.variant=STM32U3xx/U375V(E-G)I_U385VGI -GenU3.menu.pnum.GENERIC_U385VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Generic U385VGIxQ GenU3.menu.pnum.GENERIC_U385VGIXQ=Generic U385VGIxQ @@ -12769,27 +13061,27 @@ GenU3.menu.pnum.GENERIC_U385VGIXQ.upload.maximum_data_size=262144 GenU3.menu.pnum.GENERIC_U385VGIXQ.build.board=GENERIC_U385VGIXQ GenU3.menu.pnum.GENERIC_U385VGIXQ.build.product_line=STM32U385xx GenU3.menu.pnum.GENERIC_U385VGIXQ.build.variant=STM32U3xx/U375V(E-G)IxQ_U385VGIxQ -GenU3.menu.pnum.GENERIC_U385VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U3.svd +GenU3.menu.pnum.GENERIC_U385VGIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U3xx/STM32U385.svd # Upload menu GenU3.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenU3.menu.upload_method.swdMethod.upload.protocol=swd -GenU3.menu.upload_method.swdMethod.upload.options= +GenU3.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenU3.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenU3.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenU3.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenU3.menu.upload_method.jlinkMethod.upload.options= +GenU3.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenU3.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenU3.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenU3.menu.upload_method.serialMethod.upload.protocol=serial -GenU3.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenU3.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenU3.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenU3.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenU3.menu.upload_method.dfuMethod.upload.protocol=dfu -GenU3.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenU3.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenU3.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenU3.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -12969,22 +13261,22 @@ GenU5.menu.pnum.GENERIC_U5A9ZJTXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/ # Upload menu GenU5.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenU5.menu.upload_method.swdMethod.upload.protocol=swd -GenU5.menu.upload_method.swdMethod.upload.options= +GenU5.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenU5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenU5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenU5.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenU5.menu.upload_method.jlinkMethod.upload.options= +GenU5.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenU5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenU5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenU5.menu.upload_method.serialMethod.upload.protocol=serial -GenU5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenU5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenU5.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenU5.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenU5.menu.upload_method.dfuMethod.upload.protocol=dfu -GenU5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenU5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenU5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenU5.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -13110,7 +13402,7 @@ GenWB.menu.pnum.GENERIC_WB55VCYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic WB55VEQx GenWB.menu.pnum.GENERIC_WB55VEQX=Generic WB55VEQx GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_size=262144 -GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_data_size=65536 +GenWB.menu.pnum.GENERIC_WB55VEQX.upload.maximum_data_size=131072 GenWB.menu.pnum.GENERIC_WB55VEQX.build.board=GENERIC_WB55VEQX GenWB.menu.pnum.GENERIC_WB55VEQX.build.product_line=STM32WB55xx GenWB.menu.pnum.GENERIC_WB55VEQX.build.variant=STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY @@ -13128,7 +13420,7 @@ GenWB.menu.pnum.GENERIC_WB55VEYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Generic WB55VGQx GenWB.menu.pnum.GENERIC_WB55VGQX=Generic WB55VGQx GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_size=524288 -GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_data_size=65536 +GenWB.menu.pnum.GENERIC_WB55VGQX.upload.maximum_data_size=131072 GenWB.menu.pnum.GENERIC_WB55VGQX.build.board=GENERIC_WB55VGQX GenWB.menu.pnum.GENERIC_WB55VGQX.build.product_line=STM32WB55xx GenWB.menu.pnum.GENERIC_WB55VGQX.build.variant=STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY @@ -13156,22 +13448,22 @@ GenWB.menu.pnum.GENERIC_WB55VYYX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenWB.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenWB.menu.upload_method.swdMethod.upload.protocol=swd -GenWB.menu.upload_method.swdMethod.upload.options= +GenWB.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenWB.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenWB.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenWB.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenWB.menu.upload_method.jlinkMethod.upload.options= +GenWB.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenWB.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenWB.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWB.menu.upload_method.serialMethod.upload.protocol=serial -GenWB.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenWB.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenWB.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenWB.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenWB.menu.upload_method.dfuMethod.upload.protocol=dfu -GenWB.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenWB.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenWB.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenWB.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -13202,6 +13494,7 @@ GenWB0.openocd.target=stm32wb0x GenWB0.upload.address=0x10040000 GenWB0.upload.mode=hwRstPulse GenWB0.upload.start=0x10000000 +GenWB0.upload.parity=none # Generic WB05KZVx GenWB0.menu.pnum.GENERIC_WB05KZVX=Generic WB05KZVx @@ -13247,12 +13540,12 @@ GenWB0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenWB0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenWB0.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenWB0.menu.upload_method.jlinkMethod.upload.options= +GenWB0.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenWB0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenWB0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWB0.menu.upload_method.serialMethod.upload.protocol=serial -GenWB0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenWB0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenWB0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenWB0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) @@ -13300,17 +13593,17 @@ GenWBA.menu.pnum.GENERIC_WBA55CGUX.debug.svd_file={runtime.tools.STM32_SVD.path} # Upload menu GenWBA.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenWBA.menu.upload_method.swdMethod.upload.protocol=swd -GenWBA.menu.upload_method.swdMethod.upload.options= +GenWBA.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenWBA.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenWBA.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenWBA.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenWBA.menu.upload_method.jlinkMethod.upload.options= +GenWBA.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenWBA.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenWBA.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWBA.menu.upload_method.serialMethod.upload.protocol=serial -GenWBA.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenWBA.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenWBA.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenWBA.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) @@ -13321,6 +13614,94 @@ GenWBA.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) GenWBA.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap GenWBA.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload +################################################################################ +# Generic WL3 +GenWL3.name=Generic STM32WL3 series + +GenWL3.build.core=arduino +GenWL3.build.board=GenWL3 +GenWL3.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 +GenWL3.build.mcu=cortex-m0plus +GenWL3.build.series=STM32WL3x +GenWL3.build.flash_offset=0x0 +GenWL3.upload.maximum_size=0 +GenWL3.upload.maximum_data_size=0 +GenWL3.openocd.target=stm32wl3x +GenWL3.upload.address=0x10040000 +GenWL3.upload.mode=hwRstPulse +GenWL3.upload.start=0x10000000 +GenWL3.upload.parity=none + +# Generic WL33C8Vx +GenWL3.menu.pnum.GENERIC_WL33C8VX=Generic WL33C8Vx +GenWL3.menu.pnum.GENERIC_WL33C8VX.upload.maximum_size=65536 +GenWL3.menu.pnum.GENERIC_WL33C8VX.upload.maximum_data_size=16384 +GenWL3.menu.pnum.GENERIC_WL33C8VX.build.board=GENERIC_WL33C8VX +GenWL3.menu.pnum.GENERIC_WL33C8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33C8VX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +GenWL3.menu.pnum.GENERIC_WL33C8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd + +# Generic WL33C8VxX +GenWL3.menu.pnum.GENERIC_WL33C8VXX=Generic WL33C8VxX +GenWL3.menu.pnum.GENERIC_WL33C8VXX.upload.maximum_size=65536 +GenWL3.menu.pnum.GENERIC_WL33C8VXX.upload.maximum_data_size=16384 +GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.board=GENERIC_WL33C8VXX +GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +GenWL3.menu.pnum.GENERIC_WL33C8VXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd + +# Generic WL33CBVx +GenWL3.menu.pnum.GENERIC_WL33CBVX=Generic WL33CBVx +GenWL3.menu.pnum.GENERIC_WL33CBVX.upload.maximum_size=131072 +GenWL3.menu.pnum.GENERIC_WL33CBVX.upload.maximum_data_size=32768 +GenWL3.menu.pnum.GENERIC_WL33CBVX.build.board=GENERIC_WL33CBVX +GenWL3.menu.pnum.GENERIC_WL33CBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CBVX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +GenWL3.menu.pnum.GENERIC_WL33CBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd + +# Generic WL33CBVxX +GenWL3.menu.pnum.GENERIC_WL33CBVXX=Generic WL33CBVxX +GenWL3.menu.pnum.GENERIC_WL33CBVXX.upload.maximum_size=131072 +GenWL3.menu.pnum.GENERIC_WL33CBVXX.upload.maximum_data_size=32768 +GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.board=GENERIC_WL33CBVXX +GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +GenWL3.menu.pnum.GENERIC_WL33CBVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd + +# Generic WL33CCVx +GenWL3.menu.pnum.GENERIC_WL33CCVX=Generic WL33CCVx +GenWL3.menu.pnum.GENERIC_WL33CCVX.upload.maximum_size=262144 +GenWL3.menu.pnum.GENERIC_WL33CCVX.upload.maximum_data_size=32768 +GenWL3.menu.pnum.GENERIC_WL33CCVX.build.board=GENERIC_WL33CCVX +GenWL3.menu.pnum.GENERIC_WL33CCVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CCVX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +GenWL3.menu.pnum.GENERIC_WL33CCVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd + +# Generic WL33CCVxX +GenWL3.menu.pnum.GENERIC_WL33CCVXX=Generic WL33CCVxX +GenWL3.menu.pnum.GENERIC_WL33CCVXX.upload.maximum_size=262144 +GenWL3.menu.pnum.GENERIC_WL33CCVXX.upload.maximum_data_size=32768 +GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.board=GENERIC_WL33CCVXX +GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) +GenWL3.menu.pnum.GENERIC_WL33CCVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd + +# Upload menu +GenWL3.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) +GenWL3.menu.upload_method.swdMethod.upload.protocol=swd +GenWL3.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} +GenWL3.menu.upload_method.swdMethod.upload.tool=stm32CubeProg + +GenWL3.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenWL3.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenWL3.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} +GenWL3.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + +GenWL3.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) +GenWL3.menu.upload_method.serialMethod.upload.protocol=serial +GenWL3.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} +GenWL3.menu.upload_method.serialMethod.upload.tool=stm32CubeProg + ################################################################################ # Generic WL GenWL.name=Generic STM32WL series @@ -13484,22 +13865,22 @@ GenWL.menu.pnum.GENERIC_WLE5JCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu GenWL.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenWL.menu.upload_method.swdMethod.upload.protocol=swd -GenWL.menu.upload_method.swdMethod.upload.options= +GenWL.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenWL.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenWL.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenWL.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenWL.menu.upload_method.jlinkMethod.upload.options= +GenWL.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenWL.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenWL.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWL.menu.upload_method.serialMethod.upload.protocol=serial -GenWL.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenWL.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenWL.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenWL.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenWL.menu.upload_method.dfuMethod.upload.protocol=dfu -GenWL.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenWL.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenWL.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -13732,22 +14113,22 @@ GenWL.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload # Upload menu 3dprinter.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) 3dprinter.menu.upload_method.swdMethod.upload.protocol=swd -3dprinter.menu.upload_method.swdMethod.upload.options= +3dprinter.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} 3dprinter.menu.upload_method.swdMethod.upload.tool=stm32CubeProg 3dprinter.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) 3dprinter.menu.upload_method.jlinkMethod.upload.protocol=jlink -3dprinter.menu.upload_method.jlinkMethod.upload.options= +3dprinter.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} 3dprinter.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg 3dprinter.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) 3dprinter.menu.upload_method.serialMethod.upload.protocol=serial -3dprinter.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +3dprinter.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} 3dprinter.menu.upload_method.serialMethod.upload.tool=stm32CubeProg 3dprinter.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) 3dprinter.menu.upload_method.dfuMethod.upload.protocol=dfu -3dprinter.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +3dprinter.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} 3dprinter.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -13812,22 +14193,22 @@ Blues.menu.pnum.CYGNET.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4 # Upload menu Blues.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Blues.menu.upload_method.swdMethod.upload.protocol=swd -Blues.menu.upload_method.swdMethod.upload.options= +Blues.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Blues.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Blues.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Blues.menu.upload_method.jlinkMethod.upload.protocol=jlink -Blues.menu.upload_method.jlinkMethod.upload.options= +Blues.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Blues.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Blues.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Blues.menu.upload_method.serialMethod.upload.protocol=serial -Blues.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +Blues.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} Blues.menu.upload_method.serialMethod.upload.tool=stm32CubeProg Blues.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Blues.menu.upload_method.dfuMethod.upload.protocol=dfu -Blues.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Blues.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Blues.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Blues.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -13875,17 +14256,17 @@ Elecgator.menu.pnum.ETHERCAT_DUINO.debug.svd_file={runtime.tools.STM32_SVD.path} # Upload menu Elecgator.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Elecgator.menu.upload_method.swdMethod.upload.protocol=swd -Elecgator.menu.upload_method.swdMethod.upload.options= +Elecgator.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Elecgator.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Elecgator.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Elecgator.menu.upload_method.jlinkMethod.upload.protocol=jlink -Elecgator.menu.upload_method.jlinkMethod.upload.options= +Elecgator.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Elecgator.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Elecgator.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Elecgator.menu.upload_method.dfuMethod.upload.protocol=dfu -Elecgator.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Elecgator.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Elecgator.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Elecgator.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -13944,22 +14325,22 @@ ESC_board.menu.pnum.STORM32_V1_31_RC.debug.svd_file={runtime.tools.STM32_SVD.pat # Upload menu ESC_board.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) ESC_board.menu.upload_method.swdMethod.upload.protocol=swd -ESC_board.menu.upload_method.swdMethod.upload.options= +ESC_board.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} ESC_board.menu.upload_method.swdMethod.upload.tool=stm32CubeProg ESC_board.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) ESC_board.menu.upload_method.jlinkMethod.upload.protocol=jlink -ESC_board.menu.upload_method.jlinkMethod.upload.options= +ESC_board.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} ESC_board.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg ESC_board.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) ESC_board.menu.upload_method.serialMethod.upload.protocol=serial -ESC_board.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +ESC_board.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} ESC_board.menu.upload_method.serialMethod.upload.tool=stm32CubeProg ESC_board.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) ESC_board.menu.upload_method.dfuMethod.upload.protocol=dfu -ESC_board.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +ESC_board.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} ESC_board.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg ESC_board.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -14050,7 +14431,7 @@ Garatronic.menu.pnum.PYBSTICK26_PRO.debug.svd_file={runtime.tools.STM32_SVD.path # PYBSTICK26 boards upload method Garatronic.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Garatronic.menu.upload_method.dfuMethod.upload.protocol=dfu -Garatronic.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Garatronic.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Garatronic.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg ################################################################################ @@ -14115,22 +14496,22 @@ GenFlight.menu.pnum.Sparky_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/ # Upload menu GenFlight.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenFlight.menu.upload_method.swdMethod.upload.protocol=swd -GenFlight.menu.upload_method.swdMethod.upload.options= +GenFlight.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} GenFlight.menu.upload_method.swdMethod.upload.tool=stm32CubeProg GenFlight.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) GenFlight.menu.upload_method.jlinkMethod.upload.protocol=jlink -GenFlight.menu.upload_method.jlinkMethod.upload.options= +GenFlight.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} GenFlight.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg GenFlight.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenFlight.menu.upload_method.serialMethod.upload.protocol=serial -GenFlight.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenFlight.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} GenFlight.menu.upload_method.serialMethod.upload.tool=stm32CubeProg GenFlight.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) GenFlight.menu.upload_method.dfuMethod.upload.protocol=dfu -GenFlight.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenFlight.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} GenFlight.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg GenFlight.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -14196,22 +14577,22 @@ IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.debug.svd_file={runtime.tools.STM32_ # Upload menu IotContinuum.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) IotContinuum.menu.upload_method.swdMethod.upload.protocol=swd -IotContinuum.menu.upload_method.swdMethod.upload.options= +IotContinuum.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} IotContinuum.menu.upload_method.swdMethod.upload.tool=stm32CubeProg IotContinuum.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) IotContinuum.menu.upload_method.jlinkMethod.upload.protocol=jlink -IotContinuum.menu.upload_method.jlinkMethod.upload.options= +IotContinuum.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} IotContinuum.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg IotContinuum.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) IotContinuum.menu.upload_method.serialMethod.upload.protocol=serial -IotContinuum.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +IotContinuum.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} IotContinuum.menu.upload_method.serialMethod.upload.tool=stm32CubeProg IotContinuum.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) IotContinuum.menu.upload_method.dfuMethod.upload.protocol=dfu -IotContinuum.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +IotContinuum.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} IotContinuum.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg IotContinuum.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -14408,22 +14789,22 @@ LoRa.menu.pnum.WE_OCEANUS1_EV.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/ # Upload menu LoRa.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) LoRa.menu.upload_method.swdMethod.upload.protocol=swd -LoRa.menu.upload_method.swdMethod.upload.options= +LoRa.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} LoRa.menu.upload_method.swdMethod.upload.tool=stm32CubeProg LoRa.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) LoRa.menu.upload_method.jlinkMethod.upload.protocol=jlink -LoRa.menu.upload_method.jlinkMethod.upload.options= +LoRa.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} LoRa.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg LoRa.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) LoRa.menu.upload_method.serialMethod.upload.protocol=serial -LoRa.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +LoRa.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} LoRa.menu.upload_method.serialMethod.upload.tool=stm32CubeProg LoRa.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) LoRa.menu.upload_method.dfuMethod.upload.protocol=dfu -LoRa.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +LoRa.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} LoRa.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg LoRa.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -14475,22 +14856,22 @@ Midatronics.menu.upload_method.MassStorage.upload.tool=massStorageCopy Midatronics.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) Midatronics.menu.upload_method.swdMethod.upload.protocol=swd -Midatronics.menu.upload_method.swdMethod.upload.options= +Midatronics.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} Midatronics.menu.upload_method.swdMethod.upload.tool=stm32CubeProg Midatronics.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) Midatronics.menu.upload_method.jlinkMethod.upload.protocol=jlink -Midatronics.menu.upload_method.jlinkMethod.upload.options= +Midatronics.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} Midatronics.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg Midatronics.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Midatronics.menu.upload_method.serialMethod.upload.protocol=serial -Midatronics.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +Midatronics.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} Midatronics.menu.upload_method.serialMethod.upload.tool=stm32CubeProg Midatronics.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Midatronics.menu.upload_method.dfuMethod.upload.protocol=dfu -Midatronics.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +Midatronics.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} Midatronics.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg Midatronics.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -14558,22 +14939,22 @@ SparkFun.menu.pnum.MICROMOD_F405.debug.svd_file={runtime.tools.STM32_SVD.path}/s # Upload menu SparkFun.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) SparkFun.menu.upload_method.swdMethod.upload.protocol=swd -SparkFun.menu.upload_method.swdMethod.upload.options= +SparkFun.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} SparkFun.menu.upload_method.swdMethod.upload.tool=stm32CubeProg SparkFun.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) SparkFun.menu.upload_method.jlinkMethod.upload.protocol=jlink -SparkFun.menu.upload_method.jlinkMethod.upload.options= +SparkFun.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} SparkFun.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg SparkFun.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) SparkFun.menu.upload_method.serialMethod.upload.protocol=serial -SparkFun.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +SparkFun.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} SparkFun.menu.upload_method.serialMethod.upload.tool=stm32CubeProg SparkFun.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) SparkFun.menu.upload_method.dfuMethod.upload.protocol=dfu -SparkFun.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +SparkFun.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} -a {upload.address} -s {upload.start} SparkFun.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg SparkFun.menu.upload_method.bmpMethod=BMP (Black Magic Probe) @@ -14616,17 +14997,17 @@ ELV_Modular_System.menu.pnum.ELV_BM_TRX1.debug.svd_file={runtime.tools.STM32_SVD # Upload menu ELV_Modular_System.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) with Bootloader ELV_Modular_System.menu.upload_method.swdMethod.upload.protocol=swd -ELV_Modular_System.menu.upload_method.swdMethod.upload.options= +ELV_Modular_System.menu.upload_method.swdMethod.upload.options=-a {upload.address} -m {upload.mode} -s {upload.start} ELV_Modular_System.menu.upload_method.swdMethod.upload.tool=stm32CubeProg ELV_Modular_System.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) with Bootloader ELV_Modular_System.menu.upload_method.jlinkMethod.upload.protocol=jlink -ELV_Modular_System.menu.upload_method.jlinkMethod.upload.options= +ELV_Modular_System.menu.upload_method.jlinkMethod.upload.options=-a {upload.address} -s {upload.start} ELV_Modular_System.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg ELV_Modular_System.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) with Bootloader ELV_Modular_System.menu.upload_method.serialMethod.upload.protocol=serial -ELV_Modular_System.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +ELV_Modular_System.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} -a {upload.address} -s {upload.start} --parity {upload.parity} ELV_Modular_System.menu.upload_method.serialMethod.upload.tool=stm32CubeProg ################################################################################ @@ -14842,6 +15223,12 @@ GenWBA.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE GenWBA.menu.xserial.disabled=Disabled (no Serial support) GenWBA.menu.xserial.disabled.build.xSerial= +GenWL3.menu.xserial.generic=Enabled (generic 'Serial') +GenWL3.menu.xserial.none=Enabled (no generic 'Serial') +GenWL3.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +GenWL3.menu.xserial.disabled=Disabled (no Serial support) +GenWL3.menu.xserial.disabled.build.xSerial= + GenWL.menu.xserial.generic=Enabled (generic 'Serial') GenWL.menu.xserial.none=Enabled (no generic 'Serial') GenWL.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -15836,6 +16223,26 @@ GenWBA.menu.opt.ogstd.build.flags.optimize=-Og GenWBA.menu.opt.o0std=No Optimization (-O0) GenWBA.menu.opt.o0std.build.flags.optimize=-O0 +GenWL3.menu.opt.osstd=Smallest (-Os default) +GenWL3.menu.opt.oslto=Smallest (-Os) with LTO +GenWL3.menu.opt.oslto.build.flags.optimize=-Os -flto +GenWL3.menu.opt.o1std=Fast (-O1) +GenWL3.menu.opt.o1std.build.flags.optimize=-O1 +GenWL3.menu.opt.o1lto=Fast (-O1) with LTO +GenWL3.menu.opt.o1lto.build.flags.optimize=-O1 -flto +GenWL3.menu.opt.o2std=Faster (-O2) +GenWL3.menu.opt.o2std.build.flags.optimize=-O2 +GenWL3.menu.opt.o2lto=Faster (-O2) with LTO +GenWL3.menu.opt.o2lto.build.flags.optimize=-O2 -flto +GenWL3.menu.opt.o3std=Fastest (-O3) +GenWL3.menu.opt.o3std.build.flags.optimize=-O3 +GenWL3.menu.opt.o3lto=Fastest (-O3) with LTO +GenWL3.menu.opt.o3lto.build.flags.optimize=-O3 -flto +GenWL3.menu.opt.ogstd=Debug (-Og) +GenWL3.menu.opt.ogstd.build.flags.optimize=-Og +GenWL3.menu.opt.o0std=No Optimization (-O0) +GenWL3.menu.opt.o0std.build.flags.optimize=-O0 + GenWL.menu.opt.osstd=Smallest (-Os default) GenWL.menu.opt.oslto=Smallest (-Os) with LTO GenWL.menu.opt.oslto.build.flags.optimize=-Os -flto @@ -16309,6 +16716,14 @@ GenWBA.menu.dbg.enable_log.build.flags.debug= GenWBA.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) GenWBA.menu.dbg.enable_all.build.flags.debug=-g +GenWL3.menu.dbg.none=None +GenWL3.menu.dbg.enable_sym=Symbols Enabled (-g) +GenWL3.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG +GenWL3.menu.dbg.enable_log=Core logs Enabled +GenWL3.menu.dbg.enable_log.build.flags.debug= +GenWL3.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) +GenWL3.menu.dbg.enable_all.build.flags.debug=-g + GenWL.menu.dbg.none=None GenWL.menu.dbg.enable_sym=Symbols Enabled (-g) GenWL.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG @@ -16684,6 +17099,16 @@ GenWBA.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_floa GenWBA.menu.rtlib.full=Newlib Standard GenWBA.menu.rtlib.full.build.flags.ldspecs= +GenWL3.menu.rtlib.nano=Newlib Nano (default) +GenWL3.menu.rtlib.nanofp=Newlib Nano + Float Printf +GenWL3.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +GenWL3.menu.rtlib.nanofs=Newlib Nano + Float Scanf +GenWL3.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +GenWL3.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +GenWL3.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +GenWL3.menu.rtlib.full=Newlib Standard +GenWL3.menu.rtlib.full.build.flags.ldspecs= + GenWL.menu.rtlib.nano=Newlib Nano (default) GenWL.menu.rtlib.nanofp=Newlib Nano + Float Printf GenWL.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 45b9f43f7c..a5223248c9 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -4494,6 +4494,214 @@ target_compile_options(DAISY_SEED_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# DATABOARD +# ----------------------------------------------------------------------------- + +set(DATABOARD_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F1xx/F103C8T_F103CB(T-U)") +set(DATABOARD_MAXSIZE 65536) +set(DATABOARD_MAXDATASIZE 20480) +set(DATABOARD_MCU cortex-m3) +set(DATABOARD_FPCONF "-") +add_library(DATABOARD INTERFACE) +target_compile_options(DATABOARD INTERFACE + "SHELL:-DSTM32F103xB" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${DATABOARD_MCU} +) +target_compile_definitions(DATABOARD INTERFACE + "STM32F1xx" + "ARDUINO_DATABOARD" + "BOARD_NAME=\"DATABOARD\"" + "BOARD_ID=DATABOARD" + "VARIANT_H=\"variant_DATABOARD.h\"" +) +target_include_directories(DATABOARD INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F1xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ + ${DATABOARD_VARIANT_PATH} +) + +target_link_options(DATABOARD INTERFACE + "LINKER:--default-script=${DATABOARD_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=20480" + "SHELL: " + -mcpu=${DATABOARD_MCU} +) + +add_library(DATABOARD_serial_disabled INTERFACE) +target_compile_options(DATABOARD_serial_disabled INTERFACE + "SHELL:" +) +add_library(DATABOARD_serial_generic INTERFACE) +target_compile_options(DATABOARD_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(DATABOARD_serial_none INTERFACE) +target_compile_options(DATABOARD_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(DATABOARD_usb_CDC INTERFACE) +target_compile_options(DATABOARD_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(DATABOARD_usb_CDCgen INTERFACE) +target_compile_options(DATABOARD_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(DATABOARD_usb_HID INTERFACE) +target_compile_options(DATABOARD_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(DATABOARD_usb_none INTERFACE) +target_compile_options(DATABOARD_usb_none INTERFACE + "SHELL:" +) +add_library(DATABOARD_xusb_FS INTERFACE) +target_compile_options(DATABOARD_xusb_FS INTERFACE + "SHELL:" +) +add_library(DATABOARD_xusb_HS INTERFACE) +target_compile_options(DATABOARD_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(DATABOARD_xusb_HSFS INTERFACE) +target_compile_options(DATABOARD_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# DATABOARD_dfu2 +# ----------------------------------------------------------------------------- + +set(DATABOARD_dfu2_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F1xx/F103C8T_F103CB(T-U)") +set(DATABOARD_dfu2_MAXSIZE 65536) +set(DATABOARD_dfu2_MAXDATASIZE 20480) +set(DATABOARD_dfu2_MCU cortex-m3) +set(DATABOARD_dfu2_FPCONF "-") +add_library(DATABOARD_dfu2 INTERFACE) +target_compile_options(DATABOARD_dfu2 INTERFACE + "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${DATABOARD_dfu2_MCU} +) +target_compile_definitions(DATABOARD_dfu2 INTERFACE + "STM32F1xx" + "ARDUINO_DATABOARD" + "BOARD_NAME=\"DATABOARD\"" + "BOARD_ID=DATABOARD" + "VARIANT_H=\"variant_DATABOARD.h\"" +) +target_include_directories(DATABOARD_dfu2 INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F1xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ + ${DATABOARD_dfu2_VARIANT_PATH} +) + +target_link_options(DATABOARD_dfu2 INTERFACE + "LINKER:--default-script=${DATABOARD_dfu2_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x2000" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=20480" + "SHELL: " + -mcpu=${DATABOARD_dfu2_MCU} +) + + +# DATABOARD_dfuo +# ----------------------------------------------------------------------------- + +set(DATABOARD_dfuo_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F1xx/F103C8T_F103CB(T-U)") +set(DATABOARD_dfuo_MAXSIZE 65536) +set(DATABOARD_dfuo_MAXDATASIZE 20480) +set(DATABOARD_dfuo_MCU cortex-m3) +set(DATABOARD_dfuo_FPCONF "-") +add_library(DATABOARD_dfuo INTERFACE) +target_compile_options(DATABOARD_dfuo INTERFACE + "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_LEGACY_LEAF" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${DATABOARD_dfuo_MCU} +) +target_compile_definitions(DATABOARD_dfuo INTERFACE + "STM32F1xx" + "ARDUINO_DATABOARD" + "BOARD_NAME=\"DATABOARD\"" + "BOARD_ID=DATABOARD" + "VARIANT_H=\"variant_DATABOARD.h\"" +) +target_include_directories(DATABOARD_dfuo INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F1xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ + ${DATABOARD_dfuo_VARIANT_PATH} +) + +target_link_options(DATABOARD_dfuo INTERFACE + "LINKER:--default-script=${DATABOARD_dfuo_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x5000" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=20480" + "SHELL: " + -mcpu=${DATABOARD_dfuo_MCU} +) + + +# DATABOARD_hid +# ----------------------------------------------------------------------------- + +set(DATABOARD_hid_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F1xx/F103C8T_F103CB(T-U)") +set(DATABOARD_hid_MAXSIZE 65536) +set(DATABOARD_hid_MAXDATASIZE 20480) +set(DATABOARD_hid_MCU cortex-m3) +set(DATABOARD_hid_FPCONF "-") +add_library(DATABOARD_hid INTERFACE) +target_compile_options(DATABOARD_hid INTERFACE + "SHELL:-DSTM32F103xB -DHAL_UART_MODULE_ENABLED -DBL_HID" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${DATABOARD_hid_MCU} +) +target_compile_definitions(DATABOARD_hid INTERFACE + "STM32F1xx" + "ARDUINO_DATABOARD" + "BOARD_NAME=\"DATABOARD\"" + "BOARD_ID=DATABOARD" + "VARIANT_H=\"variant_DATABOARD.h\"" +) +target_include_directories(DATABOARD_hid INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F1xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F1xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/ + ${DATABOARD_hid_VARIANT_PATH} +) + +target_link_options(DATABOARD_hid INTERFACE + "LINKER:--default-script=${DATABOARD_hid_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x800" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=20480" + "SHELL: " + -mcpu=${DATABOARD_hid_MCU} +) + + # DEMO_F030F4 # ----------------------------------------------------------------------------- @@ -5332,6 +5540,88 @@ target_compile_options(DISCO_F407VG_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# DISCO_F411VE +# ----------------------------------------------------------------------------- + +set(DISCO_F411VE_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F411V(C-E)T") +set(DISCO_F411VE_MAXSIZE 524288) +set(DISCO_F411VE_MAXDATASIZE 131072) +set(DISCO_F411VE_MCU cortex-m4) +set(DISCO_F411VE_FPCONF "fpv4-sp-d16-hard") +add_library(DISCO_F411VE INTERFACE) +target_compile_options(DISCO_F411VE INTERFACE + "SHELL:-DSTM32F411xE" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${DISCO_F411VE_MCU} +) +target_compile_definitions(DISCO_F411VE INTERFACE + "STM32F4xx" + "ARDUINO_DISCO_F411VE" + "BOARD_NAME=\"DISCO_F411VE\"" + "BOARD_ID=DISCO_F411VE" + "VARIANT_H=\"variant_DISCO_F411VE.h\"" +) +target_include_directories(DISCO_F411VE INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${DISCO_F411VE_VARIANT_PATH} +) + +target_link_options(DISCO_F411VE INTERFACE + "LINKER:--default-script=${DISCO_F411VE_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${DISCO_F411VE_MCU} +) + +add_library(DISCO_F411VE_serial_disabled INTERFACE) +target_compile_options(DISCO_F411VE_serial_disabled INTERFACE + "SHELL:" +) +add_library(DISCO_F411VE_serial_generic INTERFACE) +target_compile_options(DISCO_F411VE_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(DISCO_F411VE_serial_none INTERFACE) +target_compile_options(DISCO_F411VE_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(DISCO_F411VE_usb_CDC INTERFACE) +target_compile_options(DISCO_F411VE_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(DISCO_F411VE_usb_CDCgen INTERFACE) +target_compile_options(DISCO_F411VE_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(DISCO_F411VE_usb_HID INTERFACE) +target_compile_options(DISCO_F411VE_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(DISCO_F411VE_usb_none INTERFACE) +target_compile_options(DISCO_F411VE_usb_none INTERFACE + "SHELL:" +) +add_library(DISCO_F411VE_xusb_FS INTERFACE) +target_compile_options(DISCO_F411VE_xusb_FS INTERFACE + "SHELL:" +) +add_library(DISCO_F411VE_xusb_HS INTERFACE) +target_compile_options(DISCO_F411VE_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(DISCO_F411VE_xusb_HSFS INTERFACE) +target_compile_options(DISCO_F411VE_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # DISCO_F413ZH # ----------------------------------------------------------------------------- @@ -5414,6 +5704,88 @@ target_compile_options(DISCO_F413ZH_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# DISCO_F429ZI +# ----------------------------------------------------------------------------- + +set(DISCO_F429ZI_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)") +set(DISCO_F429ZI_MAXSIZE 2097152) +set(DISCO_F429ZI_MAXDATASIZE 196608) +set(DISCO_F429ZI_MCU cortex-m4) +set(DISCO_F429ZI_FPCONF "fpv4-sp-d16-hard") +add_library(DISCO_F429ZI INTERFACE) +target_compile_options(DISCO_F429ZI INTERFACE + "SHELL:-DSTM32F429xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${DISCO_F429ZI_MCU} +) +target_compile_definitions(DISCO_F429ZI INTERFACE + "STM32F4xx" + "ARDUINO_DISCO_F429ZI" + "BOARD_NAME=\"DISCO_F429ZI\"" + "BOARD_ID=DISCO_F429ZI" + "VARIANT_H=\"variant_DISCO_F429ZI.h\"" +) +target_include_directories(DISCO_F429ZI INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${DISCO_F429ZI_VARIANT_PATH} +) + +target_link_options(DISCO_F429ZI INTERFACE + "LINKER:--default-script=${DISCO_F429ZI_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${DISCO_F429ZI_MCU} +) + +add_library(DISCO_F429ZI_serial_disabled INTERFACE) +target_compile_options(DISCO_F429ZI_serial_disabled INTERFACE + "SHELL:" +) +add_library(DISCO_F429ZI_serial_generic INTERFACE) +target_compile_options(DISCO_F429ZI_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(DISCO_F429ZI_serial_none INTERFACE) +target_compile_options(DISCO_F429ZI_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(DISCO_F429ZI_usb_CDC INTERFACE) +target_compile_options(DISCO_F429ZI_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(DISCO_F429ZI_usb_CDCgen INTERFACE) +target_compile_options(DISCO_F429ZI_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(DISCO_F429ZI_usb_HID INTERFACE) +target_compile_options(DISCO_F429ZI_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(DISCO_F429ZI_usb_none INTERFACE) +target_compile_options(DISCO_F429ZI_usb_none INTERFACE + "SHELL:" +) +add_library(DISCO_F429ZI_xusb_FS INTERFACE) +target_compile_options(DISCO_F429ZI_xusb_FS INTERFACE + "SHELL:" +) +add_library(DISCO_F429ZI_xusb_HS INTERFACE) +target_compile_options(DISCO_F429ZI_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(DISCO_F429ZI_xusb_HSFS INTERFACE) +target_compile_options(DISCO_F429ZI_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # DISCO_F746NG # ----------------------------------------------------------------------------- @@ -7338,6 +7710,286 @@ target_compile_options(GENERIC_C031F6PX_usb_none INTERFACE "SHELL:" ) +# GENERIC_C051C6TX +# ----------------------------------------------------------------------------- + +set(GENERIC_C051C6TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C051C(6-8)(T-U)") +set(GENERIC_C051C6TX_MAXSIZE 32768) +set(GENERIC_C051C6TX_MAXDATASIZE 12288) +set(GENERIC_C051C6TX_MCU cortex-m0plus) +set(GENERIC_C051C6TX_FPCONF "-") +add_library(GENERIC_C051C6TX INTERFACE) +target_compile_options(GENERIC_C051C6TX INTERFACE + "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C051C6TX_MCU} +) +target_compile_definitions(GENERIC_C051C6TX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C051C6TX" + "BOARD_NAME=\"GENERIC_C051C6TX\"" + "BOARD_ID=GENERIC_C051C6TX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C051C6TX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C051C6TX_VARIANT_PATH} +) + +target_link_options(GENERIC_C051C6TX INTERFACE + "LINKER:--default-script=${GENERIC_C051C6TX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=32768" + "LINKER:--defsym=LD_MAX_DATA_SIZE=12288" + "SHELL: " + -mcpu=${GENERIC_C051C6TX_MCU} +) + +add_library(GENERIC_C051C6TX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C051C6TX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C051C6TX_serial_generic INTERFACE) +target_compile_options(GENERIC_C051C6TX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C051C6TX_serial_none INTERFACE) +target_compile_options(GENERIC_C051C6TX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C051C6TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C051C6TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C051C6TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C051C6TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C051C6TX_usb_HID INTERFACE) +target_compile_options(GENERIC_C051C6TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C051C6TX_usb_none INTERFACE) +target_compile_options(GENERIC_C051C6TX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C051C6UX +# ----------------------------------------------------------------------------- + +set(GENERIC_C051C6UX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C051C(6-8)(T-U)") +set(GENERIC_C051C6UX_MAXSIZE 32768) +set(GENERIC_C051C6UX_MAXDATASIZE 12288) +set(GENERIC_C051C6UX_MCU cortex-m0plus) +set(GENERIC_C051C6UX_FPCONF "-") +add_library(GENERIC_C051C6UX INTERFACE) +target_compile_options(GENERIC_C051C6UX INTERFACE + "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C051C6UX_MCU} +) +target_compile_definitions(GENERIC_C051C6UX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C051C6UX" + "BOARD_NAME=\"GENERIC_C051C6UX\"" + "BOARD_ID=GENERIC_C051C6UX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C051C6UX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C051C6UX_VARIANT_PATH} +) + +target_link_options(GENERIC_C051C6UX INTERFACE + "LINKER:--default-script=${GENERIC_C051C6UX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=32768" + "LINKER:--defsym=LD_MAX_DATA_SIZE=12288" + "SHELL: " + -mcpu=${GENERIC_C051C6UX_MCU} +) + +add_library(GENERIC_C051C6UX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C051C6UX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C051C6UX_serial_generic INTERFACE) +target_compile_options(GENERIC_C051C6UX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C051C6UX_serial_none INTERFACE) +target_compile_options(GENERIC_C051C6UX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C051C6UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C051C6UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C051C6UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C051C6UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C051C6UX_usb_HID INTERFACE) +target_compile_options(GENERIC_C051C6UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C051C6UX_usb_none INTERFACE) +target_compile_options(GENERIC_C051C6UX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C051C8TX +# ----------------------------------------------------------------------------- + +set(GENERIC_C051C8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C051C(6-8)(T-U)") +set(GENERIC_C051C8TX_MAXSIZE 65536) +set(GENERIC_C051C8TX_MAXDATASIZE 12288) +set(GENERIC_C051C8TX_MCU cortex-m0plus) +set(GENERIC_C051C8TX_FPCONF "-") +add_library(GENERIC_C051C8TX INTERFACE) +target_compile_options(GENERIC_C051C8TX INTERFACE + "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C051C8TX_MCU} +) +target_compile_definitions(GENERIC_C051C8TX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C051C8TX" + "BOARD_NAME=\"GENERIC_C051C8TX\"" + "BOARD_ID=GENERIC_C051C8TX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C051C8TX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C051C8TX_VARIANT_PATH} +) + +target_link_options(GENERIC_C051C8TX INTERFACE + "LINKER:--default-script=${GENERIC_C051C8TX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=12288" + "SHELL: " + -mcpu=${GENERIC_C051C8TX_MCU} +) + +add_library(GENERIC_C051C8TX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C051C8TX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C051C8TX_serial_generic INTERFACE) +target_compile_options(GENERIC_C051C8TX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C051C8TX_serial_none INTERFACE) +target_compile_options(GENERIC_C051C8TX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C051C8TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C051C8TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C051C8TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C051C8TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C051C8TX_usb_HID INTERFACE) +target_compile_options(GENERIC_C051C8TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C051C8TX_usb_none INTERFACE) +target_compile_options(GENERIC_C051C8TX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C051C8UX +# ----------------------------------------------------------------------------- + +set(GENERIC_C051C8UX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C051C(6-8)(T-U)") +set(GENERIC_C051C8UX_MAXSIZE 65536) +set(GENERIC_C051C8UX_MAXDATASIZE 12288) +set(GENERIC_C051C8UX_MCU cortex-m0plus) +set(GENERIC_C051C8UX_FPCONF "-") +add_library(GENERIC_C051C8UX INTERFACE) +target_compile_options(GENERIC_C051C8UX INTERFACE + "SHELL:-DSTM32C051xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C051C8UX_MCU} +) +target_compile_definitions(GENERIC_C051C8UX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C051C8UX" + "BOARD_NAME=\"GENERIC_C051C8UX\"" + "BOARD_ID=GENERIC_C051C8UX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C051C8UX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C051C8UX_VARIANT_PATH} +) + +target_link_options(GENERIC_C051C8UX INTERFACE + "LINKER:--default-script=${GENERIC_C051C8UX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=12288" + "SHELL: " + -mcpu=${GENERIC_C051C8UX_MCU} +) + +add_library(GENERIC_C051C8UX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C051C8UX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C051C8UX_serial_generic INTERFACE) +target_compile_options(GENERIC_C051C8UX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C051C8UX_serial_none INTERFACE) +target_compile_options(GENERIC_C051C8UX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C051C8UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C051C8UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C051C8UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C051C8UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C051C8UX_usb_HID INTERFACE) +target_compile_options(GENERIC_C051C8UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C051C8UX_usb_none INTERFACE) +target_compile_options(GENERIC_C051C8UX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_C071G8UX # ----------------------------------------------------------------------------- @@ -7621,7 +8273,7 @@ target_compile_options(GENERIC_C071RBTX_usb_none INTERFACE # GENERIC_C092CBTX # ----------------------------------------------------------------------------- -set(GENERIC_C092CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") set(GENERIC_C092CBTX_MAXSIZE 131072) set(GENERIC_C092CBTX_MAXDATASIZE 30720) set(GENERIC_C092CBTX_MCU cortex-m0plus) @@ -7688,10 +8340,220 @@ target_compile_options(GENERIC_C092CBTX_usb_none INTERFACE "SHELL:" ) +# GENERIC_C092CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") +set(GENERIC_C092CBUX_MAXSIZE 131072) +set(GENERIC_C092CBUX_MAXDATASIZE 30720) +set(GENERIC_C092CBUX_MCU cortex-m0plus) +set(GENERIC_C092CBUX_FPCONF "-") +add_library(GENERIC_C092CBUX INTERFACE) +target_compile_options(GENERIC_C092CBUX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CBUX_MCU} +) +target_compile_definitions(GENERIC_C092CBUX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CBUX" + "BOARD_NAME=\"GENERIC_C092CBUX\"" + "BOARD_ID=GENERIC_C092CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CBUX INTERFACE + "LINKER:--default-script=${GENERIC_C092CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CBUX_MCU} +) + +add_library(GENERIC_C092CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CBUX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092CCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") +set(GENERIC_C092CCTX_MAXSIZE 262144) +set(GENERIC_C092CCTX_MAXDATASIZE 30720) +set(GENERIC_C092CCTX_MCU cortex-m0plus) +set(GENERIC_C092CCTX_FPCONF "-") +add_library(GENERIC_C092CCTX INTERFACE) +target_compile_options(GENERIC_C092CCTX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CCTX_MCU} +) +target_compile_definitions(GENERIC_C092CCTX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CCTX" + "BOARD_NAME=\"GENERIC_C092CCTX\"" + "BOARD_ID=GENERIC_C092CCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CCTX INTERFACE + "LINKER:--default-script=${GENERIC_C092CCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CCTX_MCU} +) + +add_library(GENERIC_C092CCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CCTX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CCTX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092C(B-C)(T-U)") +set(GENERIC_C092CCUX_MAXSIZE 262144) +set(GENERIC_C092CCUX_MAXDATASIZE 30720) +set(GENERIC_C092CCUX_MCU cortex-m0plus) +set(GENERIC_C092CCUX_FPCONF "-") +add_library(GENERIC_C092CCUX INTERFACE) +target_compile_options(GENERIC_C092CCUX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CCUX_MCU} +) +target_compile_definitions(GENERIC_C092CCUX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CCUX" + "BOARD_NAME=\"GENERIC_C092CCUX\"" + "BOARD_ID=GENERIC_C092CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CCUX INTERFACE + "LINKER:--default-script=${GENERIC_C092CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CCUX_MCU} +) + +add_library(GENERIC_C092CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CCUX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_C092RBTX # ----------------------------------------------------------------------------- -set(GENERIC_C092RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(GENERIC_C092RBTX_MAXSIZE 131072) set(GENERIC_C092RBTX_MAXDATASIZE 30720) set(GENERIC_C092RBTX_MCU cortex-m0plus) @@ -7761,7 +8623,7 @@ target_compile_options(GENERIC_C092RBTX_usb_none INTERFACE # GENERIC_C092RCIX # ----------------------------------------------------------------------------- -set(GENERIC_C092RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(GENERIC_C092RCIX_MAXSIZE 262144) set(GENERIC_C092RCIX_MAXDATASIZE 30720) set(GENERIC_C092RCIX_MCU cortex-m0plus) @@ -7831,7 +8693,7 @@ target_compile_options(GENERIC_C092RCIX_usb_none INTERFACE # GENERIC_C092RCTX # ----------------------------------------------------------------------------- -set(GENERIC_C092RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(GENERIC_C092RCTX_MAXSIZE 262144) set(GENERIC_C092RCTX_MAXDATASIZE 30720) set(GENERIC_C092RCTX_MCU cortex-m0plus) @@ -42472,6 +43334,254 @@ target_link_options(GENERIC_F411RETX_hid INTERFACE ) +# GENERIC_F411VCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_F411VCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F411V(C-E)T") +set(GENERIC_F411VCTX_MAXSIZE 262144) +set(GENERIC_F411VCTX_MAXDATASIZE 131072) +set(GENERIC_F411VCTX_MCU cortex-m4) +set(GENERIC_F411VCTX_FPCONF "-") +add_library(GENERIC_F411VCTX INTERFACE) +target_compile_options(GENERIC_F411VCTX INTERFACE + "SHELL:-DSTM32F411xE" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VCTX_MCU} +) +target_compile_definitions(GENERIC_F411VCTX INTERFACE + "STM32F4xx" + "ARDUINO_GENERIC_F411VCTX" + "BOARD_NAME=\"GENERIC_F411VCTX\"" + "BOARD_ID=GENERIC_F411VCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F411VCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${GENERIC_F411VCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_F411VCTX INTERFACE + "LINKER:--default-script=${GENERIC_F411VCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VCTX_MCU} +) + +add_library(GENERIC_F411VCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F411VCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F411VCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_F411VCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F411VCTX_serial_none INTERFACE) +target_compile_options(GENERIC_F411VCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F411VCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F411VCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F411VCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F411VCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F411VCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_F411VCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F411VCTX_usb_none INTERFACE) +target_compile_options(GENERIC_F411VCTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F411VCTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F411VCTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F411VCTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F411VCTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F411VCTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F411VCTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F411VCTX_hid +# ----------------------------------------------------------------------------- + +set(GENERIC_F411VCTX_hid_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F411V(C-E)T") +set(GENERIC_F411VCTX_hid_MAXSIZE 262144) +set(GENERIC_F411VCTX_hid_MAXDATASIZE 131072) +set(GENERIC_F411VCTX_hid_MCU cortex-m4) +set(GENERIC_F411VCTX_hid_FPCONF "-") +add_library(GENERIC_F411VCTX_hid INTERFACE) +target_compile_options(GENERIC_F411VCTX_hid INTERFACE + "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VCTX_hid_MCU} +) +target_compile_definitions(GENERIC_F411VCTX_hid INTERFACE + "STM32F4xx" + "ARDUINO_GENERIC_F411VCTX" + "BOARD_NAME=\"GENERIC_F411VCTX\"" + "BOARD_ID=GENERIC_F411VCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F411VCTX_hid INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${GENERIC_F411VCTX_hid_VARIANT_PATH} +) + +target_link_options(GENERIC_F411VCTX_hid INTERFACE + "LINKER:--default-script=${GENERIC_F411VCTX_hid_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x4000" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VCTX_hid_MCU} +) + + +# GENERIC_F411VETX +# ----------------------------------------------------------------------------- + +set(GENERIC_F411VETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F411V(C-E)T") +set(GENERIC_F411VETX_MAXSIZE 524288) +set(GENERIC_F411VETX_MAXDATASIZE 131072) +set(GENERIC_F411VETX_MCU cortex-m4) +set(GENERIC_F411VETX_FPCONF "-") +add_library(GENERIC_F411VETX INTERFACE) +target_compile_options(GENERIC_F411VETX INTERFACE + "SHELL:-DSTM32F411xE" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VETX_MCU} +) +target_compile_definitions(GENERIC_F411VETX INTERFACE + "STM32F4xx" + "ARDUINO_GENERIC_F411VETX" + "BOARD_NAME=\"GENERIC_F411VETX\"" + "BOARD_ID=GENERIC_F411VETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F411VETX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${GENERIC_F411VETX_VARIANT_PATH} +) + +target_link_options(GENERIC_F411VETX INTERFACE + "LINKER:--default-script=${GENERIC_F411VETX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VETX_MCU} +) + +add_library(GENERIC_F411VETX_serial_disabled INTERFACE) +target_compile_options(GENERIC_F411VETX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_F411VETX_serial_generic INTERFACE) +target_compile_options(GENERIC_F411VETX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_F411VETX_serial_none INTERFACE) +target_compile_options(GENERIC_F411VETX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_F411VETX_usb_CDC INTERFACE) +target_compile_options(GENERIC_F411VETX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_F411VETX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_F411VETX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_F411VETX_usb_HID INTERFACE) +target_compile_options(GENERIC_F411VETX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_F411VETX_usb_none INTERFACE) +target_compile_options(GENERIC_F411VETX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_F411VETX_xusb_FS INTERFACE) +target_compile_options(GENERIC_F411VETX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_F411VETX_xusb_HS INTERFACE) +target_compile_options(GENERIC_F411VETX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_F411VETX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_F411VETX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_F411VETX_hid +# ----------------------------------------------------------------------------- + +set(GENERIC_F411VETX_hid_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F411V(C-E)T") +set(GENERIC_F411VETX_hid_MAXSIZE 524288) +set(GENERIC_F411VETX_hid_MAXDATASIZE 131072) +set(GENERIC_F411VETX_hid_MCU cortex-m4) +set(GENERIC_F411VETX_hid_FPCONF "-") +add_library(GENERIC_F411VETX_hid INTERFACE) +target_compile_options(GENERIC_F411VETX_hid INTERFACE + "SHELL:-DSTM32F411xE -DHAL_UART_MODULE_ENABLED -DBL_HID" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VETX_hid_MCU} +) +target_compile_definitions(GENERIC_F411VETX_hid INTERFACE + "STM32F4xx" + "ARDUINO_GENERIC_F411VETX" + "BOARD_NAME=\"GENERIC_F411VETX\"" + "BOARD_ID=GENERIC_F411VETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_F411VETX_hid INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${GENERIC_F411VETX_hid_VARIANT_PATH} +) + +target_link_options(GENERIC_F411VETX_hid INTERFACE + "LINKER:--default-script=${GENERIC_F411VETX_hid_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x4000" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_F411VETX_hid_MCU} +) + + # GENERIC_F412CEUX # ----------------------------------------------------------------------------- @@ -73767,7 +74877,7 @@ target_compile_options(GENERIC_G484VETX_xusb_HSFS INTERFACE set(GENERIC_G491CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491C(C-E)T_G4A1CET") set(GENERIC_G491CCTX_MAXSIZE 262144) -set(GENERIC_G491CCTX_MAXDATASIZE 131072) +set(GENERIC_G491CCTX_MAXDATASIZE 114688) set(GENERIC_G491CCTX_MCU cortex-m4) set(GENERIC_G491CCTX_FPCONF "-") add_library(GENERIC_G491CCTX INTERFACE) @@ -73798,7 +74908,7 @@ target_link_options(GENERIC_G491CCTX INTERFACE "LINKER:--default-script=${GENERIC_G491CCTX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491CCTX_MCU} ) @@ -73849,7 +74959,7 @@ target_compile_options(GENERIC_G491CCTX_xusb_HSFS INTERFACE set(GENERIC_G491CETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491C(C-E)T_G4A1CET") set(GENERIC_G491CETX_MAXSIZE 524288) -set(GENERIC_G491CETX_MAXDATASIZE 131072) +set(GENERIC_G491CETX_MAXDATASIZE 114688) set(GENERIC_G491CETX_MCU cortex-m4) set(GENERIC_G491CETX_FPCONF "-") add_library(GENERIC_G491CETX INTERFACE) @@ -73880,7 +74990,7 @@ target_link_options(GENERIC_G491CETX INTERFACE "LINKER:--default-script=${GENERIC_G491CETX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491CETX_MCU} ) @@ -73931,7 +75041,7 @@ target_compile_options(GENERIC_G491CETX_xusb_HSFS INTERFACE set(GENERIC_G491KCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491K(C-E)U_G4A1KEU") set(GENERIC_G491KCUX_MAXSIZE 262144) -set(GENERIC_G491KCUX_MAXDATASIZE 131072) +set(GENERIC_G491KCUX_MAXDATASIZE 114688) set(GENERIC_G491KCUX_MCU cortex-m4) set(GENERIC_G491KCUX_FPCONF "-") add_library(GENERIC_G491KCUX INTERFACE) @@ -73962,7 +75072,7 @@ target_link_options(GENERIC_G491KCUX INTERFACE "LINKER:--default-script=${GENERIC_G491KCUX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491KCUX_MCU} ) @@ -74013,7 +75123,7 @@ target_compile_options(GENERIC_G491KCUX_xusb_HSFS INTERFACE set(GENERIC_G491KEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491K(C-E)U_G4A1KEU") set(GENERIC_G491KEUX_MAXSIZE 524288) -set(GENERIC_G491KEUX_MAXDATASIZE 131072) +set(GENERIC_G491KEUX_MAXDATASIZE 114688) set(GENERIC_G491KEUX_MCU cortex-m4) set(GENERIC_G491KEUX_FPCONF "-") add_library(GENERIC_G491KEUX INTERFACE) @@ -74044,7 +75154,7 @@ target_link_options(GENERIC_G491KEUX INTERFACE "LINKER:--default-script=${GENERIC_G491KEUX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491KEUX_MCU} ) @@ -74095,7 +75205,7 @@ target_compile_options(GENERIC_G491KEUX_xusb_HSFS INTERFACE set(GENERIC_G491MCSX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)") set(GENERIC_G491MCSX_MAXSIZE 262144) -set(GENERIC_G491MCSX_MAXDATASIZE 131072) +set(GENERIC_G491MCSX_MAXDATASIZE 114688) set(GENERIC_G491MCSX_MCU cortex-m4) set(GENERIC_G491MCSX_FPCONF "-") add_library(GENERIC_G491MCSX INTERFACE) @@ -74126,7 +75236,7 @@ target_link_options(GENERIC_G491MCSX INTERFACE "LINKER:--default-script=${GENERIC_G491MCSX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491MCSX_MCU} ) @@ -74177,7 +75287,7 @@ target_compile_options(GENERIC_G491MCSX_xusb_HSFS INTERFACE set(GENERIC_G491MCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)") set(GENERIC_G491MCTX_MAXSIZE 262144) -set(GENERIC_G491MCTX_MAXDATASIZE 131072) +set(GENERIC_G491MCTX_MAXDATASIZE 114688) set(GENERIC_G491MCTX_MCU cortex-m4) set(GENERIC_G491MCTX_FPCONF "-") add_library(GENERIC_G491MCTX INTERFACE) @@ -74208,7 +75318,7 @@ target_link_options(GENERIC_G491MCTX INTERFACE "LINKER:--default-script=${GENERIC_G491MCTX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491MCTX_MCU} ) @@ -74259,7 +75369,7 @@ target_compile_options(GENERIC_G491MCTX_xusb_HSFS INTERFACE set(GENERIC_G491MESX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)") set(GENERIC_G491MESX_MAXSIZE 524288) -set(GENERIC_G491MESX_MAXDATASIZE 131072) +set(GENERIC_G491MESX_MAXDATASIZE 114688) set(GENERIC_G491MESX_MCU cortex-m4) set(GENERIC_G491MESX_FPCONF "-") add_library(GENERIC_G491MESX INTERFACE) @@ -74290,7 +75400,7 @@ target_link_options(GENERIC_G491MESX INTERFACE "LINKER:--default-script=${GENERIC_G491MESX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491MESX_MCU} ) @@ -74341,7 +75451,7 @@ target_compile_options(GENERIC_G491MESX_xusb_HSFS INTERFACE set(GENERIC_G491METX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)") set(GENERIC_G491METX_MAXSIZE 524288) -set(GENERIC_G491METX_MAXDATASIZE 131072) +set(GENERIC_G491METX_MAXDATASIZE 114688) set(GENERIC_G491METX_MCU cortex-m4) set(GENERIC_G491METX_FPCONF "-") add_library(GENERIC_G491METX INTERFACE) @@ -74372,7 +75482,7 @@ target_link_options(GENERIC_G491METX INTERFACE "LINKER:--default-script=${GENERIC_G491METX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491METX_MCU} ) @@ -74423,7 +75533,7 @@ target_compile_options(GENERIC_G491METX_xusb_HSFS INTERFACE set(GENERIC_G491RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RCIX_MAXSIZE 262144) -set(GENERIC_G491RCIX_MAXDATASIZE 131072) +set(GENERIC_G491RCIX_MAXDATASIZE 114688) set(GENERIC_G491RCIX_MCU cortex-m4) set(GENERIC_G491RCIX_FPCONF "-") add_library(GENERIC_G491RCIX INTERFACE) @@ -74454,7 +75564,7 @@ target_link_options(GENERIC_G491RCIX INTERFACE "LINKER:--default-script=${GENERIC_G491RCIX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RCIX_MCU} ) @@ -74505,7 +75615,7 @@ target_compile_options(GENERIC_G491RCIX_xusb_HSFS INTERFACE set(GENERIC_G491RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RCTX_MAXSIZE 262144) -set(GENERIC_G491RCTX_MAXDATASIZE 131072) +set(GENERIC_G491RCTX_MAXDATASIZE 114688) set(GENERIC_G491RCTX_MCU cortex-m4) set(GENERIC_G491RCTX_FPCONF "-") add_library(GENERIC_G491RCTX INTERFACE) @@ -74536,7 +75646,7 @@ target_link_options(GENERIC_G491RCTX INTERFACE "LINKER:--default-script=${GENERIC_G491RCTX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RCTX_MCU} ) @@ -74587,7 +75697,7 @@ target_compile_options(GENERIC_G491RCTX_xusb_HSFS INTERFACE set(GENERIC_G491REIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491REIX_MAXSIZE 524288) -set(GENERIC_G491REIX_MAXDATASIZE 131072) +set(GENERIC_G491REIX_MAXDATASIZE 114688) set(GENERIC_G491REIX_MCU cortex-m4) set(GENERIC_G491REIX_FPCONF "-") add_library(GENERIC_G491REIX INTERFACE) @@ -74618,7 +75728,7 @@ target_link_options(GENERIC_G491REIX INTERFACE "LINKER:--default-script=${GENERIC_G491REIX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491REIX_MCU} ) @@ -74669,7 +75779,7 @@ target_compile_options(GENERIC_G491REIX_xusb_HSFS INTERFACE set(GENERIC_G491RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RETX_MAXSIZE 524288) -set(GENERIC_G491RETX_MAXDATASIZE 131072) +set(GENERIC_G491RETX_MAXDATASIZE 114688) set(GENERIC_G491RETX_MCU cortex-m4) set(GENERIC_G491RETX_FPCONF "-") add_library(GENERIC_G491RETX INTERFACE) @@ -74700,7 +75810,7 @@ target_link_options(GENERIC_G491RETX INTERFACE "LINKER:--default-script=${GENERIC_G491RETX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RETX_MCU} ) @@ -74751,7 +75861,7 @@ target_compile_options(GENERIC_G491RETX_xusb_HSFS INTERFACE set(GENERIC_G491RETXZ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RETXZ_MAXSIZE 524288) -set(GENERIC_G491RETXZ_MAXDATASIZE 131072) +set(GENERIC_G491RETXZ_MAXDATASIZE 114688) set(GENERIC_G491RETXZ_MCU cortex-m4) set(GENERIC_G491RETXZ_FPCONF "-") add_library(GENERIC_G491RETXZ INTERFACE) @@ -74782,7 +75892,7 @@ target_link_options(GENERIC_G491RETXZ INTERFACE "LINKER:--default-script=${GENERIC_G491RETXZ_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491RETXZ_MCU} ) @@ -74833,7 +75943,7 @@ target_compile_options(GENERIC_G491RETXZ_xusb_HSFS INTERFACE set(GENERIC_G491REYX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491REYX_MAXSIZE 524288) -set(GENERIC_G491REYX_MAXDATASIZE 131072) +set(GENERIC_G491REYX_MAXDATASIZE 114688) set(GENERIC_G491REYX_MCU cortex-m4) set(GENERIC_G491REYX_FPCONF "-") add_library(GENERIC_G491REYX INTERFACE) @@ -74864,7 +75974,7 @@ target_link_options(GENERIC_G491REYX INTERFACE "LINKER:--default-script=${GENERIC_G491REYX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491REYX_MCU} ) @@ -74915,7 +76025,7 @@ target_compile_options(GENERIC_G491REYX_xusb_HSFS INTERFACE set(GENERIC_G491VCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491V(C-E)T_G4A1VET") set(GENERIC_G491VCTX_MAXSIZE 262144) -set(GENERIC_G491VCTX_MAXDATASIZE 131072) +set(GENERIC_G491VCTX_MAXDATASIZE 114688) set(GENERIC_G491VCTX_MCU cortex-m4) set(GENERIC_G491VCTX_FPCONF "-") add_library(GENERIC_G491VCTX INTERFACE) @@ -74946,7 +76056,7 @@ target_link_options(GENERIC_G491VCTX INTERFACE "LINKER:--default-script=${GENERIC_G491VCTX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491VCTX_MCU} ) @@ -74997,7 +76107,7 @@ target_compile_options(GENERIC_G491VCTX_xusb_HSFS INTERFACE set(GENERIC_G491VETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491V(C-E)T_G4A1VET") set(GENERIC_G491VETX_MAXSIZE 524288) -set(GENERIC_G491VETX_MAXDATASIZE 131072) +set(GENERIC_G491VETX_MAXDATASIZE 114688) set(GENERIC_G491VETX_MCU cortex-m4) set(GENERIC_G491VETX_FPCONF "-") add_library(GENERIC_G491VETX INTERFACE) @@ -75028,7 +76138,7 @@ target_link_options(GENERIC_G491VETX INTERFACE "LINKER:--default-script=${GENERIC_G491VETX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G491VETX_MCU} ) @@ -75079,7 +76189,7 @@ target_compile_options(GENERIC_G491VETX_xusb_HSFS INTERFACE set(GENERIC_G4A1CETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491C(C-E)T_G4A1CET") set(GENERIC_G4A1CETX_MAXSIZE 524288) -set(GENERIC_G4A1CETX_MAXDATASIZE 131072) +set(GENERIC_G4A1CETX_MAXDATASIZE 114688) set(GENERIC_G4A1CETX_MCU cortex-m4) set(GENERIC_G4A1CETX_FPCONF "-") add_library(GENERIC_G4A1CETX INTERFACE) @@ -75110,7 +76220,7 @@ target_link_options(GENERIC_G4A1CETX INTERFACE "LINKER:--default-script=${GENERIC_G4A1CETX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1CETX_MCU} ) @@ -75161,7 +76271,7 @@ target_compile_options(GENERIC_G4A1CETX_xusb_HSFS INTERFACE set(GENERIC_G4A1KEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491K(C-E)U_G4A1KEU") set(GENERIC_G4A1KEUX_MAXSIZE 524288) -set(GENERIC_G4A1KEUX_MAXDATASIZE 131072) +set(GENERIC_G4A1KEUX_MAXDATASIZE 114688) set(GENERIC_G4A1KEUX_MCU cortex-m4) set(GENERIC_G4A1KEUX_FPCONF "-") add_library(GENERIC_G4A1KEUX INTERFACE) @@ -75192,7 +76302,7 @@ target_link_options(GENERIC_G4A1KEUX INTERFACE "LINKER:--default-script=${GENERIC_G4A1KEUX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1KEUX_MCU} ) @@ -75243,7 +76353,7 @@ target_compile_options(GENERIC_G4A1KEUX_xusb_HSFS INTERFACE set(GENERIC_G4A1MESX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)") set(GENERIC_G4A1MESX_MAXSIZE 524288) -set(GENERIC_G4A1MESX_MAXDATASIZE 131072) +set(GENERIC_G4A1MESX_MAXDATASIZE 114688) set(GENERIC_G4A1MESX_MCU cortex-m4) set(GENERIC_G4A1MESX_FPCONF "-") add_library(GENERIC_G4A1MESX INTERFACE) @@ -75274,7 +76384,7 @@ target_link_options(GENERIC_G4A1MESX INTERFACE "LINKER:--default-script=${GENERIC_G4A1MESX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1MESX_MCU} ) @@ -75325,7 +76435,7 @@ target_compile_options(GENERIC_G4A1MESX_xusb_HSFS INTERFACE set(GENERIC_G4A1METX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)") set(GENERIC_G4A1METX_MAXSIZE 524288) -set(GENERIC_G4A1METX_MAXDATASIZE 131072) +set(GENERIC_G4A1METX_MAXDATASIZE 114688) set(GENERIC_G4A1METX_MCU cortex-m4) set(GENERIC_G4A1METX_FPCONF "-") add_library(GENERIC_G4A1METX INTERFACE) @@ -75356,7 +76466,7 @@ target_link_options(GENERIC_G4A1METX INTERFACE "LINKER:--default-script=${GENERIC_G4A1METX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1METX_MCU} ) @@ -75407,7 +76517,7 @@ target_compile_options(GENERIC_G4A1METX_xusb_HSFS INTERFACE set(GENERIC_G4A1REIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G4A1REIX_MAXSIZE 524288) -set(GENERIC_G4A1REIX_MAXDATASIZE 131072) +set(GENERIC_G4A1REIX_MAXDATASIZE 114688) set(GENERIC_G4A1REIX_MCU cortex-m4) set(GENERIC_G4A1REIX_FPCONF "-") add_library(GENERIC_G4A1REIX INTERFACE) @@ -75438,7 +76548,7 @@ target_link_options(GENERIC_G4A1REIX INTERFACE "LINKER:--default-script=${GENERIC_G4A1REIX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1REIX_MCU} ) @@ -75489,7 +76599,7 @@ target_compile_options(GENERIC_G4A1REIX_xusb_HSFS INTERFACE set(GENERIC_G4A1RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G4A1RETX_MAXSIZE 524288) -set(GENERIC_G4A1RETX_MAXDATASIZE 131072) +set(GENERIC_G4A1RETX_MAXDATASIZE 114688) set(GENERIC_G4A1RETX_MCU cortex-m4) set(GENERIC_G4A1RETX_FPCONF "-") add_library(GENERIC_G4A1RETX INTERFACE) @@ -75520,7 +76630,7 @@ target_link_options(GENERIC_G4A1RETX INTERFACE "LINKER:--default-script=${GENERIC_G4A1RETX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1RETX_MCU} ) @@ -75571,7 +76681,7 @@ target_compile_options(GENERIC_G4A1RETX_xusb_HSFS INTERFACE set(GENERIC_G4A1REYX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G4A1REYX_MAXSIZE 524288) -set(GENERIC_G4A1REYX_MAXDATASIZE 131072) +set(GENERIC_G4A1REYX_MAXDATASIZE 114688) set(GENERIC_G4A1REYX_MCU cortex-m4) set(GENERIC_G4A1REYX_FPCONF "-") add_library(GENERIC_G4A1REYX INTERFACE) @@ -75602,7 +76712,7 @@ target_link_options(GENERIC_G4A1REYX INTERFACE "LINKER:--default-script=${GENERIC_G4A1REYX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1REYX_MCU} ) @@ -75653,7 +76763,7 @@ target_compile_options(GENERIC_G4A1REYX_xusb_HSFS INTERFACE set(GENERIC_G4A1VETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491V(C-E)T_G4A1VET") set(GENERIC_G4A1VETX_MAXSIZE 524288) -set(GENERIC_G4A1VETX_MAXDATASIZE 131072) +set(GENERIC_G4A1VETX_MAXDATASIZE 114688) set(GENERIC_G4A1VETX_MCU cortex-m4) set(GENERIC_G4A1VETX_FPCONF "-") add_library(GENERIC_G4A1VETX INTERFACE) @@ -75684,7 +76794,7 @@ target_link_options(GENERIC_G4A1VETX INTERFACE "LINKER:--default-script=${GENERIC_G4A1VETX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=114688" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_G4A1VETX_MCU} ) @@ -76878,6 +77988,334 @@ target_compile_options(GENERIC_H573ZITX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H723VEHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H723VEHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H723VEHX_MAXSIZE 524288) +set(GENERIC_H723VEHX_MAXDATASIZE 528384) +set(GENERIC_H723VEHX_MCU cortex-m7) +set(GENERIC_H723VEHX_FPCONF "-") +add_library(GENERIC_H723VEHX INTERFACE) +target_compile_options(GENERIC_H723VEHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H723xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VEHX_MCU} +) +target_compile_definitions(GENERIC_H723VEHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H723VEHX" + "BOARD_NAME=\"GENERIC_H723VEHX\"" + "BOARD_ID=GENERIC_H723VEHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H723VEHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H723VEHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H723VEHX INTERFACE + "LINKER:--default-script=${GENERIC_H723VEHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VEHX_MCU} +) + +add_library(GENERIC_H723VEHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H723VEHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VEHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H723VEHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H723VEHX_serial_none INTERFACE) +target_compile_options(GENERIC_H723VEHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H723VEHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H723VEHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H723VEHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H723VEHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H723VEHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H723VEHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H723VEHX_usb_none INTERFACE) +target_compile_options(GENERIC_H723VEHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VEHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H723VEHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VEHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H723VEHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H723VEHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H723VEHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H723VETX +# ----------------------------------------------------------------------------- + +set(GENERIC_H723VETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H723VETX_MAXSIZE 524288) +set(GENERIC_H723VETX_MAXDATASIZE 528384) +set(GENERIC_H723VETX_MCU cortex-m7) +set(GENERIC_H723VETX_FPCONF "-") +add_library(GENERIC_H723VETX INTERFACE) +target_compile_options(GENERIC_H723VETX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H723xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VETX_MCU} +) +target_compile_definitions(GENERIC_H723VETX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H723VETX" + "BOARD_NAME=\"GENERIC_H723VETX\"" + "BOARD_ID=GENERIC_H723VETX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H723VETX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H723VETX_VARIANT_PATH} +) + +target_link_options(GENERIC_H723VETX INTERFACE + "LINKER:--default-script=${GENERIC_H723VETX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VETX_MCU} +) + +add_library(GENERIC_H723VETX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H723VETX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VETX_serial_generic INTERFACE) +target_compile_options(GENERIC_H723VETX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H723VETX_serial_none INTERFACE) +target_compile_options(GENERIC_H723VETX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H723VETX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H723VETX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H723VETX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H723VETX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H723VETX_usb_HID INTERFACE) +target_compile_options(GENERIC_H723VETX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H723VETX_usb_none INTERFACE) +target_compile_options(GENERIC_H723VETX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VETX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H723VETX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VETX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H723VETX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H723VETX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H723VETX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H723VGHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H723VGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H723VGHX_MAXSIZE 1048576) +set(GENERIC_H723VGHX_MAXDATASIZE 528384) +set(GENERIC_H723VGHX_MCU cortex-m7) +set(GENERIC_H723VGHX_FPCONF "-") +add_library(GENERIC_H723VGHX INTERFACE) +target_compile_options(GENERIC_H723VGHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H723xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VGHX_MCU} +) +target_compile_definitions(GENERIC_H723VGHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H723VGHX" + "BOARD_NAME=\"GENERIC_H723VGHX\"" + "BOARD_ID=GENERIC_H723VGHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H723VGHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H723VGHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H723VGHX INTERFACE + "LINKER:--default-script=${GENERIC_H723VGHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VGHX_MCU} +) + +add_library(GENERIC_H723VGHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H723VGHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VGHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H723VGHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H723VGHX_serial_none INTERFACE) +target_compile_options(GENERIC_H723VGHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H723VGHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H723VGHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H723VGHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H723VGHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H723VGHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H723VGHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H723VGHX_usb_none INTERFACE) +target_compile_options(GENERIC_H723VGHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VGHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H723VGHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VGHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H723VGHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H723VGHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H723VGHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H723VGTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H723VGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H723VGTX_MAXSIZE 1048576) +set(GENERIC_H723VGTX_MAXDATASIZE 528384) +set(GENERIC_H723VGTX_MCU cortex-m7) +set(GENERIC_H723VGTX_FPCONF "-") +add_library(GENERIC_H723VGTX INTERFACE) +target_compile_options(GENERIC_H723VGTX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H723xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VGTX_MCU} +) +target_compile_definitions(GENERIC_H723VGTX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H723VGTX" + "BOARD_NAME=\"GENERIC_H723VGTX\"" + "BOARD_ID=GENERIC_H723VGTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H723VGTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H723VGTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H723VGTX INTERFACE + "LINKER:--default-script=${GENERIC_H723VGTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H723VGTX_MCU} +) + +add_library(GENERIC_H723VGTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H723VGTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VGTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H723VGTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H723VGTX_serial_none INTERFACE) +target_compile_options(GENERIC_H723VGTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H723VGTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H723VGTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H723VGTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H723VGTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H723VGTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H723VGTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H723VGTX_usb_none INTERFACE) +target_compile_options(GENERIC_H723VGTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VGTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H723VGTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H723VGTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H723VGTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H723VGTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H723VGTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H723ZETX # ----------------------------------------------------------------------------- @@ -77042,6 +78480,170 @@ target_compile_options(GENERIC_H723ZGTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H730VBHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H730VBHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H730VBHX_MAXSIZE 131072) +set(GENERIC_H730VBHX_MAXDATASIZE 528384) +set(GENERIC_H730VBHX_MCU cortex-m7) +set(GENERIC_H730VBHX_FPCONF "-") +add_library(GENERIC_H730VBHX INTERFACE) +target_compile_options(GENERIC_H730VBHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H730xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H730VBHX_MCU} +) +target_compile_definitions(GENERIC_H730VBHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H730VBHX" + "BOARD_NAME=\"GENERIC_H730VBHX\"" + "BOARD_ID=GENERIC_H730VBHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H730VBHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H730VBHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H730VBHX INTERFACE + "LINKER:--default-script=${GENERIC_H730VBHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H730VBHX_MCU} +) + +add_library(GENERIC_H730VBHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H730VBHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H730VBHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H730VBHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H730VBHX_serial_none INTERFACE) +target_compile_options(GENERIC_H730VBHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H730VBHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H730VBHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H730VBHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H730VBHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H730VBHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H730VBHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H730VBHX_usb_none INTERFACE) +target_compile_options(GENERIC_H730VBHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H730VBHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H730VBHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H730VBHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H730VBHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H730VBHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H730VBHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H730VBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H730VBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H730VBTX_MAXSIZE 131072) +set(GENERIC_H730VBTX_MAXDATASIZE 528384) +set(GENERIC_H730VBTX_MCU cortex-m7) +set(GENERIC_H730VBTX_FPCONF "-") +add_library(GENERIC_H730VBTX INTERFACE) +target_compile_options(GENERIC_H730VBTX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H730xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H730VBTX_MCU} +) +target_compile_definitions(GENERIC_H730VBTX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H730VBTX" + "BOARD_NAME=\"GENERIC_H730VBTX\"" + "BOARD_ID=GENERIC_H730VBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H730VBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H730VBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H730VBTX INTERFACE + "LINKER:--default-script=${GENERIC_H730VBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H730VBTX_MCU} +) + +add_library(GENERIC_H730VBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H730VBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H730VBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H730VBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H730VBTX_serial_none INTERFACE) +target_compile_options(GENERIC_H730VBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H730VBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H730VBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H730VBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H730VBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H730VBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H730VBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H730VBTX_usb_none INTERFACE) +target_compile_options(GENERIC_H730VBTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H730VBTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H730VBTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H730VBTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H730VBTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H730VBTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H730VBTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H730ZBTX # ----------------------------------------------------------------------------- @@ -77124,6 +78726,170 @@ target_compile_options(GENERIC_H730ZBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H733VGHX +# ----------------------------------------------------------------------------- + +set(GENERIC_H733VGHX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H733VGHX_MAXSIZE 1048576) +set(GENERIC_H733VGHX_MAXDATASIZE 528384) +set(GENERIC_H733VGHX_MCU cortex-m7) +set(GENERIC_H733VGHX_FPCONF "-") +add_library(GENERIC_H733VGHX INTERFACE) +target_compile_options(GENERIC_H733VGHX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H733xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H733VGHX_MCU} +) +target_compile_definitions(GENERIC_H733VGHX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H733VGHX" + "BOARD_NAME=\"GENERIC_H733VGHX\"" + "BOARD_ID=GENERIC_H733VGHX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H733VGHX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H733VGHX_VARIANT_PATH} +) + +target_link_options(GENERIC_H733VGHX INTERFACE + "LINKER:--default-script=${GENERIC_H733VGHX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H733VGHX_MCU} +) + +add_library(GENERIC_H733VGHX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H733VGHX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H733VGHX_serial_generic INTERFACE) +target_compile_options(GENERIC_H733VGHX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H733VGHX_serial_none INTERFACE) +target_compile_options(GENERIC_H733VGHX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H733VGHX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H733VGHX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H733VGHX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H733VGHX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H733VGHX_usb_HID INTERFACE) +target_compile_options(GENERIC_H733VGHX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H733VGHX_usb_none INTERFACE) +target_compile_options(GENERIC_H733VGHX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H733VGHX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H733VGHX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H733VGHX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H733VGHX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H733VGHX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H733VGHX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H733VGTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H733VGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(GENERIC_H733VGTX_MAXSIZE 1048576) +set(GENERIC_H733VGTX_MAXDATASIZE 528384) +set(GENERIC_H733VGTX_MCU cortex-m7) +set(GENERIC_H733VGTX_FPCONF "-") +add_library(GENERIC_H733VGTX INTERFACE) +target_compile_options(GENERIC_H733VGTX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H733xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H733VGTX_MCU} +) +target_compile_definitions(GENERIC_H733VGTX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H733VGTX" + "BOARD_NAME=\"GENERIC_H733VGTX\"" + "BOARD_ID=GENERIC_H733VGTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H733VGTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H733VGTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H733VGTX INTERFACE + "LINKER:--default-script=${GENERIC_H733VGTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=528384" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H733VGTX_MCU} +) + +add_library(GENERIC_H733VGTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H733VGTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H733VGTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H733VGTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H733VGTX_serial_none INTERFACE) +target_compile_options(GENERIC_H733VGTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H733VGTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H733VGTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H733VGTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H733VGTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H733VGTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H733VGTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H733VGTX_usb_none INTERFACE) +target_compile_options(GENERIC_H733VGTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H733VGTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H733VGTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H733VGTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H733VGTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H733VGTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H733VGTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H733ZGTX # ----------------------------------------------------------------------------- @@ -79338,6 +81104,88 @@ target_compile_options(GENERIC_H745XIHX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H745ZITX +# ----------------------------------------------------------------------------- + +set(GENERIC_H745ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H745Z(G-I)T_H755ZIT") +set(GENERIC_H745ZITX_MAXSIZE 2097152) +set(GENERIC_H745ZITX_MAXDATASIZE 884736) +set(GENERIC_H745ZITX_MCU cortex-m7) +set(GENERIC_H745ZITX_FPCONF "-") +add_library(GENERIC_H745ZITX INTERFACE) +target_compile_options(GENERIC_H745ZITX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H745xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745ZITX_MCU} +) +target_compile_definitions(GENERIC_H745ZITX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H745ZITX" + "BOARD_NAME=\"GENERIC_H745ZITX\"" + "BOARD_ID=GENERIC_H745ZITX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H745ZITX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H745ZITX_VARIANT_PATH} +) + +target_link_options(GENERIC_H745ZITX INTERFACE + "LINKER:--default-script=${GENERIC_H745ZITX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=884736" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745ZITX_MCU} +) + +add_library(GENERIC_H745ZITX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H745ZITX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H745ZITX_serial_generic INTERFACE) +target_compile_options(GENERIC_H745ZITX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H745ZITX_serial_none INTERFACE) +target_compile_options(GENERIC_H745ZITX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H745ZITX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H745ZITX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H745ZITX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H745ZITX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H745ZITX_usb_HID INTERFACE) +target_compile_options(GENERIC_H745ZITX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H745ZITX_usb_none INTERFACE) +target_compile_options(GENERIC_H745ZITX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H745ZITX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H745ZITX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H745ZITX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H745ZITX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H745ZITX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H745ZITX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H747AGIX # ----------------------------------------------------------------------------- @@ -101238,6 +103086,426 @@ target_compile_options(GENERIC_NODE_SE_TTI_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +# GENERIC_U073C8TX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073C8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073C8TX_MAXSIZE 65536) +set(GENERIC_U073C8TX_MAXDATASIZE 40960) +set(GENERIC_U073C8TX_MCU cortex-m0plus) +set(GENERIC_U073C8TX_FPCONF "-") +add_library(GENERIC_U073C8TX INTERFACE) +target_compile_options(GENERIC_U073C8TX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073C8TX_MCU} +) +target_compile_definitions(GENERIC_U073C8TX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073C8TX" + "BOARD_NAME=\"GENERIC_U073C8TX\"" + "BOARD_ID=GENERIC_U073C8TX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073C8TX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073C8TX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073C8TX INTERFACE + "LINKER:--default-script=${GENERIC_U073C8TX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073C8TX_MCU} +) + +add_library(GENERIC_U073C8TX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073C8TX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073C8TX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073C8TX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073C8TX_serial_none INTERFACE) +target_compile_options(GENERIC_U073C8TX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073C8TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073C8TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073C8TX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073C8TX_usb_none INTERFACE) +target_compile_options(GENERIC_U073C8TX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073C8UX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073C8UX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073C8UX_MAXSIZE 65536) +set(GENERIC_U073C8UX_MAXDATASIZE 40960) +set(GENERIC_U073C8UX_MCU cortex-m0plus) +set(GENERIC_U073C8UX_FPCONF "-") +add_library(GENERIC_U073C8UX INTERFACE) +target_compile_options(GENERIC_U073C8UX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073C8UX_MCU} +) +target_compile_definitions(GENERIC_U073C8UX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073C8UX" + "BOARD_NAME=\"GENERIC_U073C8UX\"" + "BOARD_ID=GENERIC_U073C8UX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073C8UX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073C8UX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073C8UX INTERFACE + "LINKER:--default-script=${GENERIC_U073C8UX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073C8UX_MCU} +) + +add_library(GENERIC_U073C8UX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073C8UX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073C8UX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073C8UX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073C8UX_serial_none INTERFACE) +target_compile_options(GENERIC_U073C8UX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073C8UX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073C8UX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073C8UX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073C8UX_usb_none INTERFACE) +target_compile_options(GENERIC_U073C8UX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CBTX_MAXSIZE 131072) +set(GENERIC_U073CBTX_MAXDATASIZE 40960) +set(GENERIC_U073CBTX_MCU cortex-m0plus) +set(GENERIC_U073CBTX_FPCONF "-") +add_library(GENERIC_U073CBTX INTERFACE) +target_compile_options(GENERIC_U073CBTX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CBTX_MCU} +) +target_compile_definitions(GENERIC_U073CBTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CBTX" + "BOARD_NAME=\"GENERIC_U073CBTX\"" + "BOARD_ID=GENERIC_U073CBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CBTX INTERFACE + "LINKER:--default-script=${GENERIC_U073CBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CBTX_MCU} +) + +add_library(GENERIC_U073CBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CBTX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CBTX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CBTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CBUX_MAXSIZE 131072) +set(GENERIC_U073CBUX_MAXDATASIZE 40960) +set(GENERIC_U073CBUX_MCU cortex-m0plus) +set(GENERIC_U073CBUX_FPCONF "-") +add_library(GENERIC_U073CBUX INTERFACE) +target_compile_options(GENERIC_U073CBUX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CBUX_MCU} +) +target_compile_definitions(GENERIC_U073CBUX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CBUX" + "BOARD_NAME=\"GENERIC_U073CBUX\"" + "BOARD_ID=GENERIC_U073CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CBUX INTERFACE + "LINKER:--default-script=${GENERIC_U073CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CBUX_MCU} +) + +add_library(GENERIC_U073CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CBUX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CCTX_MAXSIZE 262144) +set(GENERIC_U073CCTX_MAXDATASIZE 40960) +set(GENERIC_U073CCTX_MCU cortex-m0plus) +set(GENERIC_U073CCTX_FPCONF "-") +add_library(GENERIC_U073CCTX INTERFACE) +target_compile_options(GENERIC_U073CCTX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CCTX_MCU} +) +target_compile_definitions(GENERIC_U073CCTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CCTX" + "BOARD_NAME=\"GENERIC_U073CCTX\"" + "BOARD_ID=GENERIC_U073CCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CCTX INTERFACE + "LINKER:--default-script=${GENERIC_U073CCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CCTX_MCU} +) + +add_library(GENERIC_U073CCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CCTX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CCTX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U073CCUX_MAXSIZE 262144) +set(GENERIC_U073CCUX_MAXDATASIZE 40960) +set(GENERIC_U073CCUX_MCU cortex-m0plus) +set(GENERIC_U073CCUX_FPCONF "-") +add_library(GENERIC_U073CCUX INTERFACE) +target_compile_options(GENERIC_U073CCUX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073CCUX_MCU} +) +target_compile_definitions(GENERIC_U073CCUX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073CCUX" + "BOARD_NAME=\"GENERIC_U073CCUX\"" + "BOARD_ID=GENERIC_U073CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073CCUX INTERFACE + "LINKER:--default-script=${GENERIC_U073CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073CCUX_MCU} +) + +add_library(GENERIC_U073CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_U073CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_U073CCUX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_U073R8IX # ----------------------------------------------------------------------------- @@ -101658,6 +103926,146 @@ target_compile_options(GENERIC_U073RCTX_usb_none INTERFACE "SHELL:" ) +# GENERIC_U083CCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U083CCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U083CCTX_MAXSIZE 262144) +set(GENERIC_U083CCTX_MAXDATASIZE 40960) +set(GENERIC_U083CCTX_MCU cortex-m0plus) +set(GENERIC_U083CCTX_FPCONF "-") +add_library(GENERIC_U083CCTX INTERFACE) +target_compile_options(GENERIC_U083CCTX INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U083CCTX_MCU} +) +target_compile_definitions(GENERIC_U083CCTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U083CCTX" + "BOARD_NAME=\"GENERIC_U083CCTX\"" + "BOARD_ID=GENERIC_U083CCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U083CCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U083CCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U083CCTX INTERFACE + "LINKER:--default-script=${GENERIC_U083CCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U083CCTX_MCU} +) + +add_library(GENERIC_U083CCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U083CCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U083CCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U083CCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U083CCTX_serial_none INTERFACE) +target_compile_options(GENERIC_U083CCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U083CCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U083CCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U083CCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U083CCTX_usb_none INTERFACE) +target_compile_options(GENERIC_U083CCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U083CCUX +# ----------------------------------------------------------------------------- + +set(GENERIC_U083CCUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073C(8-B-C)(T-U)_U083CC(T-U)") +set(GENERIC_U083CCUX_MAXSIZE 262144) +set(GENERIC_U083CCUX_MAXDATASIZE 40960) +set(GENERIC_U083CCUX_MCU cortex-m0plus) +set(GENERIC_U083CCUX_FPCONF "-") +add_library(GENERIC_U083CCUX INTERFACE) +target_compile_options(GENERIC_U083CCUX INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U083CCUX_MCU} +) +target_compile_definitions(GENERIC_U083CCUX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U083CCUX" + "BOARD_NAME=\"GENERIC_U083CCUX\"" + "BOARD_ID=GENERIC_U083CCUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U083CCUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U083CCUX_VARIANT_PATH} +) + +target_link_options(GENERIC_U083CCUX INTERFACE + "LINKER:--default-script=${GENERIC_U083CCUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U083CCUX_MCU} +) + +add_library(GENERIC_U083CCUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U083CCUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U083CCUX_serial_generic INTERFACE) +target_compile_options(GENERIC_U083CCUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U083CCUX_serial_none INTERFACE) +target_compile_options(GENERIC_U083CCUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U083CCUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U083CCUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U083CCUX_usb_HID INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U083CCUX_usb_none INTERFACE) +target_compile_options(GENERIC_U083CCUX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_U083RCIX # ----------------------------------------------------------------------------- @@ -104699,7 +107107,7 @@ target_compile_options(GENERIC_WB55VCYX_xusb_HSFS INTERFACE set(GENERIC_WB55VEQX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY") set(GENERIC_WB55VEQX_MAXSIZE 262144) -set(GENERIC_WB55VEQX_MAXDATASIZE 65536) +set(GENERIC_WB55VEQX_MAXDATASIZE 131072) set(GENERIC_WB55VEQX_MCU cortex-m4) set(GENERIC_WB55VEQX_FPCONF "-") add_library(GENERIC_WB55VEQX INTERFACE) @@ -104730,7 +107138,7 @@ target_link_options(GENERIC_WB55VEQX INTERFACE "LINKER:--default-script=${GENERIC_WB55VEQX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=262144" - "LINKER:--defsym=LD_MAX_DATA_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VEQX_MCU} ) @@ -104863,7 +107271,7 @@ target_compile_options(GENERIC_WB55VEYX_xusb_HSFS INTERFACE set(GENERIC_WB55VGQX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBxx/WB55V(C-E-G)(Q-Y)_WB55VYY") set(GENERIC_WB55VGQX_MAXSIZE 524288) -set(GENERIC_WB55VGQX_MAXDATASIZE 65536) +set(GENERIC_WB55VGQX_MAXDATASIZE 131072) set(GENERIC_WB55VGQX_MCU cortex-m4) set(GENERIC_WB55VGQX_FPCONF "-") add_library(GENERIC_WB55VGQX INTERFACE) @@ -104894,7 +107302,7 @@ target_link_options(GENERIC_WB55VGQX INTERFACE "LINKER:--default-script=${GENERIC_WB55VGQX_VARIANT_PATH}/ldscript.ld" "LINKER:--defsym=LD_FLASH_OFFSET=0x0" "LINKER:--defsym=LD_MAX_SIZE=524288" - "LINKER:--defsym=LD_MAX_DATA_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" -mcpu=${GENERIC_WB55VGQX_MCU} ) @@ -105294,6 +107702,330 @@ target_compile_options(GENERIC_WBA55CGUX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +# GENERIC_WL33C8VX +# ----------------------------------------------------------------------------- + +set(GENERIC_WL33C8VX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(GENERIC_WL33C8VX_MAXSIZE 65536) +set(GENERIC_WL33C8VX_MAXDATASIZE 16384) +set(GENERIC_WL33C8VX_MCU cortex-m0plus) +set(GENERIC_WL33C8VX_FPCONF "-") +add_library(GENERIC_WL33C8VX INTERFACE) +target_compile_options(GENERIC_WL33C8VX INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_WL33C8VX_MCU} +) +target_compile_definitions(GENERIC_WL33C8VX INTERFACE + "STM32WL3x" + "ARDUINO_GENERIC_WL33C8VX" + "BOARD_NAME=\"GENERIC_WL33C8VX\"" + "BOARD_ID=GENERIC_WL33C8VX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WL33C8VX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${GENERIC_WL33C8VX_VARIANT_PATH} +) + +target_link_options(GENERIC_WL33C8VX INTERFACE + "LINKER:--default-script=${GENERIC_WL33C8VX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=16384" + "SHELL: " + -mcpu=${GENERIC_WL33C8VX_MCU} +) + +add_library(GENERIC_WL33C8VX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WL33C8VX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WL33C8VX_serial_generic INTERFACE) +target_compile_options(GENERIC_WL33C8VX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WL33C8VX_serial_none INTERFACE) +target_compile_options(GENERIC_WL33C8VX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_WL33C8VXX +# ----------------------------------------------------------------------------- + +set(GENERIC_WL33C8VXX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(GENERIC_WL33C8VXX_MAXSIZE 65536) +set(GENERIC_WL33C8VXX_MAXDATASIZE 16384) +set(GENERIC_WL33C8VXX_MCU cortex-m0plus) +set(GENERIC_WL33C8VXX_FPCONF "-") +add_library(GENERIC_WL33C8VXX INTERFACE) +target_compile_options(GENERIC_WL33C8VXX INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_WL33C8VXX_MCU} +) +target_compile_definitions(GENERIC_WL33C8VXX INTERFACE + "STM32WL3x" + "ARDUINO_GENERIC_WL33C8VXX" + "BOARD_NAME=\"GENERIC_WL33C8VXX\"" + "BOARD_ID=GENERIC_WL33C8VXX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WL33C8VXX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${GENERIC_WL33C8VXX_VARIANT_PATH} +) + +target_link_options(GENERIC_WL33C8VXX INTERFACE + "LINKER:--default-script=${GENERIC_WL33C8VXX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=16384" + "SHELL: " + -mcpu=${GENERIC_WL33C8VXX_MCU} +) + +add_library(GENERIC_WL33C8VXX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WL33C8VXX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WL33C8VXX_serial_generic INTERFACE) +target_compile_options(GENERIC_WL33C8VXX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WL33C8VXX_serial_none INTERFACE) +target_compile_options(GENERIC_WL33C8VXX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_WL33CBVX +# ----------------------------------------------------------------------------- + +set(GENERIC_WL33CBVX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(GENERIC_WL33CBVX_MAXSIZE 131072) +set(GENERIC_WL33CBVX_MAXDATASIZE 32768) +set(GENERIC_WL33CBVX_MCU cortex-m0plus) +set(GENERIC_WL33CBVX_FPCONF "-") +add_library(GENERIC_WL33CBVX INTERFACE) +target_compile_options(GENERIC_WL33CBVX INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_WL33CBVX_MCU} +) +target_compile_definitions(GENERIC_WL33CBVX INTERFACE + "STM32WL3x" + "ARDUINO_GENERIC_WL33CBVX" + "BOARD_NAME=\"GENERIC_WL33CBVX\"" + "BOARD_ID=GENERIC_WL33CBVX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WL33CBVX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${GENERIC_WL33CBVX_VARIANT_PATH} +) + +target_link_options(GENERIC_WL33CBVX INTERFACE + "LINKER:--default-script=${GENERIC_WL33CBVX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL: " + -mcpu=${GENERIC_WL33CBVX_MCU} +) + +add_library(GENERIC_WL33CBVX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WL33CBVX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WL33CBVX_serial_generic INTERFACE) +target_compile_options(GENERIC_WL33CBVX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WL33CBVX_serial_none INTERFACE) +target_compile_options(GENERIC_WL33CBVX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_WL33CBVXX +# ----------------------------------------------------------------------------- + +set(GENERIC_WL33CBVXX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(GENERIC_WL33CBVXX_MAXSIZE 131072) +set(GENERIC_WL33CBVXX_MAXDATASIZE 32768) +set(GENERIC_WL33CBVXX_MCU cortex-m0plus) +set(GENERIC_WL33CBVXX_FPCONF "-") +add_library(GENERIC_WL33CBVXX INTERFACE) +target_compile_options(GENERIC_WL33CBVXX INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_WL33CBVXX_MCU} +) +target_compile_definitions(GENERIC_WL33CBVXX INTERFACE + "STM32WL3x" + "ARDUINO_GENERIC_WL33CBVXX" + "BOARD_NAME=\"GENERIC_WL33CBVXX\"" + "BOARD_ID=GENERIC_WL33CBVXX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WL33CBVXX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${GENERIC_WL33CBVXX_VARIANT_PATH} +) + +target_link_options(GENERIC_WL33CBVXX INTERFACE + "LINKER:--default-script=${GENERIC_WL33CBVXX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL: " + -mcpu=${GENERIC_WL33CBVXX_MCU} +) + +add_library(GENERIC_WL33CBVXX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WL33CBVXX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WL33CBVXX_serial_generic INTERFACE) +target_compile_options(GENERIC_WL33CBVXX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WL33CBVXX_serial_none INTERFACE) +target_compile_options(GENERIC_WL33CBVXX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_WL33CCVX +# ----------------------------------------------------------------------------- + +set(GENERIC_WL33CCVX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(GENERIC_WL33CCVX_MAXSIZE 262144) +set(GENERIC_WL33CCVX_MAXDATASIZE 32768) +set(GENERIC_WL33CCVX_MCU cortex-m0plus) +set(GENERIC_WL33CCVX_FPCONF "-") +add_library(GENERIC_WL33CCVX INTERFACE) +target_compile_options(GENERIC_WL33CCVX INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_WL33CCVX_MCU} +) +target_compile_definitions(GENERIC_WL33CCVX INTERFACE + "STM32WL3x" + "ARDUINO_GENERIC_WL33CCVX" + "BOARD_NAME=\"GENERIC_WL33CCVX\"" + "BOARD_ID=GENERIC_WL33CCVX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WL33CCVX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${GENERIC_WL33CCVX_VARIANT_PATH} +) + +target_link_options(GENERIC_WL33CCVX INTERFACE + "LINKER:--default-script=${GENERIC_WL33CCVX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL: " + -mcpu=${GENERIC_WL33CCVX_MCU} +) + +add_library(GENERIC_WL33CCVX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WL33CCVX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WL33CCVX_serial_generic INTERFACE) +target_compile_options(GENERIC_WL33CCVX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WL33CCVX_serial_none INTERFACE) +target_compile_options(GENERIC_WL33CCVX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_WL33CCVXX +# ----------------------------------------------------------------------------- + +set(GENERIC_WL33CCVXX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(GENERIC_WL33CCVXX_MAXSIZE 262144) +set(GENERIC_WL33CCVXX_MAXDATASIZE 32768) +set(GENERIC_WL33CCVXX_MCU cortex-m0plus) +set(GENERIC_WL33CCVXX_FPCONF "-") +add_library(GENERIC_WL33CCVXX INTERFACE) +target_compile_options(GENERIC_WL33CCVXX INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_WL33CCVXX_MCU} +) +target_compile_definitions(GENERIC_WL33CCVXX INTERFACE + "STM32WL3x" + "ARDUINO_GENERIC_WL33CCVXX" + "BOARD_NAME=\"GENERIC_WL33CCVXX\"" + "BOARD_ID=GENERIC_WL33CCVXX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WL33CCVXX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${GENERIC_WL33CCVXX_VARIANT_PATH} +) + +target_link_options(GENERIC_WL33CCVXX INTERFACE + "LINKER:--default-script=${GENERIC_WL33CCVXX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL: " + -mcpu=${GENERIC_WL33CCVXX_MCU} +) + +add_library(GENERIC_WL33CCVXX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WL33CCVXX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WL33CCVXX_serial_generic INTERFACE) +target_compile_options(GENERIC_WL33CCVXX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WL33CCVXX_serial_none INTERFACE) +target_compile_options(GENERIC_WL33CCVXX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + # GENERIC_WL54CCUX # ----------------------------------------------------------------------------- @@ -107275,7 +110007,7 @@ target_compile_options(NUCLEO_C071RB_xusb_HSFS INTERFACE # NUCLEO_C092RC # ----------------------------------------------------------------------------- -set(NUCLEO_C092RC_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(NUCLEO_C092RC_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092RBT_C092RC(I-T)") set(NUCLEO_C092RC_MAXSIZE 262144) set(NUCLEO_C092RC_MAXDATASIZE 30720) set(NUCLEO_C092RC_MCU cortex-m0plus) @@ -108256,6 +110988,88 @@ target_compile_options(NUCLEO_F303RE_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_F334R8 +# ----------------------------------------------------------------------------- + +set(NUCLEO_F334R8_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F3xx/F303R(6-8)T_F334R(6-8)T") +set(NUCLEO_F334R8_MAXSIZE 65536) +set(NUCLEO_F334R8_MAXDATASIZE 12288) +set(NUCLEO_F334R8_MCU cortex-m4) +set(NUCLEO_F334R8_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_F334R8 INTERFACE) +target_compile_options(NUCLEO_F334R8 INTERFACE + "SHELL:-DSTM32F334x8" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_F334R8_MCU} +) +target_compile_definitions(NUCLEO_F334R8 INTERFACE + "STM32F3xx" + "ARDUINO_NUCLEO_F334R8" + "BOARD_NAME=\"NUCLEO_F334R8\"" + "BOARD_ID=NUCLEO_F334R8" + "VARIANT_H=\"variant_NUCLEO_F334R8.h\"" +) +target_include_directories(NUCLEO_F334R8 INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F3xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F3xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/ + ${NUCLEO_F334R8_VARIANT_PATH} +) + +target_link_options(NUCLEO_F334R8 INTERFACE + "LINKER:--default-script=${NUCLEO_F334R8_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=12288" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_F334R8_MCU} +) + +add_library(NUCLEO_F334R8_serial_disabled INTERFACE) +target_compile_options(NUCLEO_F334R8_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_F334R8_serial_generic INTERFACE) +target_compile_options(NUCLEO_F334R8_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_F334R8_serial_none INTERFACE) +target_compile_options(NUCLEO_F334R8_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_F334R8_usb_CDC INTERFACE) +target_compile_options(NUCLEO_F334R8_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_F334R8_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_F334R8_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_F334R8_usb_HID INTERFACE) +target_compile_options(NUCLEO_F334R8_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_F334R8_usb_none INTERFACE) +target_compile_options(NUCLEO_F334R8_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_F334R8_xusb_FS INTERFACE) +target_compile_options(NUCLEO_F334R8_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_F334R8_xusb_HS INTERFACE) +target_compile_options(NUCLEO_F334R8_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_F334R8_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_F334R8_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_F401RE # ----------------------------------------------------------------------------- @@ -110306,6 +113120,88 @@ target_compile_options(NUCLEO_H743ZI2_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_H745ZI_Q +# ----------------------------------------------------------------------------- + +set(NUCLEO_H745ZI_Q_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H745Z(G-I)T_H755ZIT") +set(NUCLEO_H745ZI_Q_MAXSIZE 2097152) +set(NUCLEO_H745ZI_Q_MAXDATASIZE 884736) +set(NUCLEO_H745ZI_Q_MCU cortex-m7) +set(NUCLEO_H745ZI_Q_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_H745ZI_Q INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q INTERFACE + "SHELL:-DSTM32H745xx -DCORE_CM7" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H745ZI_Q_MCU} +) +target_compile_definitions(NUCLEO_H745ZI_Q INTERFACE + "STM32H7xx" + "ARDUINO_NUCLEO_H745ZI_Q" + "BOARD_NAME=\"NUCLEO_H745ZI_Q\"" + "BOARD_ID=NUCLEO_H745ZI_Q" + "VARIANT_H=\"variant_NUCLEO_H745ZI_Q.h\"" +) +target_include_directories(NUCLEO_H745ZI_Q INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${NUCLEO_H745ZI_Q_VARIANT_PATH} +) + +target_link_options(NUCLEO_H745ZI_Q INTERFACE + "LINKER:--default-script=${NUCLEO_H745ZI_Q_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=884736" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_H745ZI_Q_MCU} +) + +add_library(NUCLEO_H745ZI_Q_serial_disabled INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_H745ZI_Q_serial_generic INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_H745ZI_Q_serial_none INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_H745ZI_Q_usb_CDC INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_H745ZI_Q_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_H745ZI_Q_usb_HID INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_H745ZI_Q_usb_none INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_H745ZI_Q_xusb_FS INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_H745ZI_Q_xusb_HS INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_H745ZI_Q_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_H745ZI_Q_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_H753ZI # ----------------------------------------------------------------------------- @@ -112438,6 +115334,170 @@ target_compile_options(NUCLEO_WBA55CG_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_WL33CC1 +# ----------------------------------------------------------------------------- + +set(NUCLEO_WL33CC1_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(NUCLEO_WL33CC1_MAXSIZE 262144) +set(NUCLEO_WL33CC1_MAXDATASIZE 32768) +set(NUCLEO_WL33CC1_MCU cortex-m0plus) +set(NUCLEO_WL33CC1_FPCONF "-") +add_library(NUCLEO_WL33CC1 INTERFACE) +target_compile_options(NUCLEO_WL33CC1 INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${NUCLEO_WL33CC1_MCU} +) +target_compile_definitions(NUCLEO_WL33CC1 INTERFACE + "STM32WL3x" + "ARDUINO_NUCLEO_WL33CC1" + "BOARD_NAME=\"NUCLEO_WL33CC1\"" + "BOARD_ID=NUCLEO_WL33CC1" + "VARIANT_H=\"variant_NUCLEO_WL33CCx.h\"" +) +target_include_directories(NUCLEO_WL33CC1 INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${NUCLEO_WL33CC1_VARIANT_PATH} +) + +target_link_options(NUCLEO_WL33CC1 INTERFACE + "LINKER:--default-script=${NUCLEO_WL33CC1_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL: " + -mcpu=${NUCLEO_WL33CC1_MCU} +) + +add_library(NUCLEO_WL33CC1_serial_disabled INTERFACE) +target_compile_options(NUCLEO_WL33CC1_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_WL33CC1_serial_generic INTERFACE) +target_compile_options(NUCLEO_WL33CC1_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_WL33CC1_serial_none INTERFACE) +target_compile_options(NUCLEO_WL33CC1_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_WL33CC1_usb_CDC INTERFACE) +target_compile_options(NUCLEO_WL33CC1_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_WL33CC1_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_WL33CC1_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_WL33CC1_usb_HID INTERFACE) +target_compile_options(NUCLEO_WL33CC1_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_WL33CC1_usb_none INTERFACE) +target_compile_options(NUCLEO_WL33CC1_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_WL33CC1_xusb_FS INTERFACE) +target_compile_options(NUCLEO_WL33CC1_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_WL33CC1_xusb_HS INTERFACE) +target_compile_options(NUCLEO_WL33CC1_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_WL33CC1_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_WL33CC1_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# NUCLEO_WL33CC2 +# ----------------------------------------------------------------------------- + +set(NUCLEO_WL33CC2_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WL3x/WL33C(8-B-C)Vx(X)") +set(NUCLEO_WL33CC2_MAXSIZE 262144) +set(NUCLEO_WL33CC2_MAXDATASIZE 32768) +set(NUCLEO_WL33CC2_MCU cortex-m0plus) +set(NUCLEO_WL33CC2_FPCONF "-") +add_library(NUCLEO_WL33CC2 INTERFACE) +target_compile_options(NUCLEO_WL33CC2 INTERFACE + "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${NUCLEO_WL33CC2_MCU} +) +target_compile_definitions(NUCLEO_WL33CC2 INTERFACE + "STM32WL3x" + "ARDUINO_NUCLEO_WL33CC2" + "BOARD_NAME=\"NUCLEO_WL33CC2\"" + "BOARD_ID=NUCLEO_WL33CC2" + "VARIANT_H=\"variant_NUCLEO_WL33CCx.h\"" +) +target_include_directories(NUCLEO_WL33CC2 INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WL3x + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WL3x_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/ + ${NUCLEO_WL33CC2_VARIANT_PATH} +) + +target_link_options(NUCLEO_WL33CC2 INTERFACE + "LINKER:--default-script=${NUCLEO_WL33CC2_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL: " + -mcpu=${NUCLEO_WL33CC2_MCU} +) + +add_library(NUCLEO_WL33CC2_serial_disabled INTERFACE) +target_compile_options(NUCLEO_WL33CC2_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_WL33CC2_serial_generic INTERFACE) +target_compile_options(NUCLEO_WL33CC2_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_WL33CC2_serial_none INTERFACE) +target_compile_options(NUCLEO_WL33CC2_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_WL33CC2_usb_CDC INTERFACE) +target_compile_options(NUCLEO_WL33CC2_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_WL33CC2_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_WL33CC2_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_WL33CC2_usb_HID INTERFACE) +target_compile_options(NUCLEO_WL33CC2_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_WL33CC2_usb_none INTERFACE) +target_compile_options(NUCLEO_WL33CC2_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_WL33CC2_xusb_FS INTERFACE) +target_compile_options(NUCLEO_WL33CC2_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_WL33CC2_xusb_HS INTERFACE) +target_compile_options(NUCLEO_WL33CC2_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_WL33CC2_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_WL33CC2_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_WL55JC1 # ----------------------------------------------------------------------------- diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index ef044ca832..84d3554da5 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -518,6 +518,8 @@ #define CMSIS_STARTUP_FILE "startup_stm32wb55xx_cm4.s" #elif defined(STM32WB5Mxx) #define CMSIS_STARTUP_FILE "startup_stm32wb5mxx_cm4.s" + #elif defined(STM32WL3xx) + #define CMSIS_STARTUP_FILE "startup_stm32wl3xx.s" #elif defined(STM32WL54xx) && defined(USE_CM0PLUS_STARTUP_FILE) #define CMSIS_STARTUP_FILE "startup_stm32wl54xx_cm0plus.s" #elif defined(STM32WL54xx) && defined(USE_CM4_STARTUP_FILE) diff --git a/libraries/EEPROM/src/utility/stm32_eeprom.c b/libraries/EEPROM/src/utility/stm32_eeprom.c index 1c26d1600b..e101556b1c 100644 --- a/libraries/EEPROM/src/utility/stm32_eeprom.c +++ b/libraries/EEPROM/src/utility/stm32_eeprom.c @@ -54,8 +54,8 @@ extern "C" { /* Be able to change EEPROM_FLASH_PAGE_NUMBER to use if relevant */ #if !defined(EEPROM_FLASH_PAGE_NUMBER) && defined(FLASH_PAGE_SIZE) -#if defined(STM32WB0x) -/* STM32WB0x define the FLASH_PAGE_NUMBER */ +#if defined(STM32WB0x) || defined(STM32WL3x) +/* STM32WB0x and STM32WL3 define the FLASH_PAGE_NUMBER */ #define EEPROM_FLASH_PAGE_NUMBER (FLASH_PAGE_NUMBER - 1) #else #define EEPROM_FLASH_PAGE_NUMBER ((uint32_t)(((LL_GetFlashSize() * 1024) / FLASH_PAGE_SIZE) - 1)) @@ -265,8 +265,9 @@ void eeprom_buffer_flush(void) EraseInitStruct.PageAddress = FLASH_BASE_ADDRESS; #endif EraseInitStruct.NbPages = 1; -#if !defined(PROT_LEVEL_NONE) +#if !defined(PROT_LEVEL_NONE) && !defined(STM32WL3x) if (HAL_FLASH_Unlock() == HAL_OK) + /* TODO: else HAL_FLASHEx_PageProtection? */ #endif { __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); @@ -303,9 +304,9 @@ void eeprom_buffer_flush(void) } } } -#if !defined(PROT_LEVEL_NONE) +#if !defined(PROT_LEVEL_NONE) && !defined(STM32WL3x) HAL_FLASH_Lock(); -#endif /* FLASH_KEY1 || FLASH_PEKEY1 */ +#endif } #else /* FLASH_TYPEERASE_SECTORS */ uint32_t SectorError = 0; diff --git a/libraries/IWatchdog/src/IWatchdog.cpp b/libraries/IWatchdog/src/IWatchdog.cpp index 7351deba35..0daf3dc512 100644 --- a/libraries/IWatchdog/src/IWatchdog.cpp +++ b/libraries/IWatchdog/src/IWatchdog.cpp @@ -182,6 +182,8 @@ bool IWatchdogClass::isReset(bool clear) bool status = LL_RCC_IsActiveFlag_IWDG1RST(); #elif defined(STM32WB0x) bool status = LL_RCC_IsActiveFlag_WDGRST(); +#elif defined(STM32WL3x) + bool status = ((RAM_VR.ResetReason & RCC_FLAG_WDGRST) == RCC_FLAG_WDGRST); #else bool status = LL_RCC_IsActiveFlag_IWDGRST(); #endif diff --git a/libraries/SPI/keywords.txt b/libraries/SPI/keywords.txt index 18701284e0..4bf7e9bc16 100644 --- a/libraries/SPI/keywords.txt +++ b/libraries/SPI/keywords.txt @@ -30,5 +30,8 @@ SPI_MODE1 LITERAL1 SPI_MODE2 LITERAL1 SPI_MODE3 LITERAL1 -SPI_CONTINUE LITERAL1 -SPI_LAST LITERAL1 +SPI_TRANSMITRECEIVE LITERAL1 +SPI_TRANSMITONLY LITERAL1 +SPI_MASTER LITERAL1 +SPI_SLAVE LITERAL1 + diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index f77b48c59b..3e6253c70d 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -46,28 +46,28 @@ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) /** * @brief Initialize the SPI instance. + * @param device: device mode (optional), SPI_MASTER or SPI_SLAVE. Default is master. */ -void SPIClass::begin(void) +void SPIClass::begin(SPIDeviceMode device) { _spi.handle.State = HAL_SPI_STATE_RESET; _spiSettings = SPISettings(); - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + _spiSettings.deviceMode = device; + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** * @brief This function should be used to configure the SPI instance in case you * don't use the default parameters set by the begin() function. - * @param settings: SPI settings(clock speed, bit order, data mode). + * @param settings: SPI settings(clock speed, bit order, data mode, device mode). */ void SPIClass::beginTransaction(SPISettings settings) { if (_spiSettings != settings) { _spiSettings = settings; - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } } @@ -96,9 +96,8 @@ void SPIClass::setBitOrder(BitOrder bitOrder) { _spiSettings.bitOrder = bitOrder; - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** @@ -120,9 +119,8 @@ void SPIClass::setDataMode(uint8_t mode) void SPIClass::setDataMode(SPIMode mode) { _spiSettings.dataMode = mode; - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** @@ -140,9 +138,8 @@ void SPIClass::setClockDivider(uint8_t divider) _spiSettings.clockFreq = spi_getClkFreq(&_spi) / divider; } - spi_init(&_spi, _spiSettings.clockFreq, - _spiSettings.dataMode, - _spiSettings.bitOrder); + spi_init(&_spi, _spiSettings.clockFreq, _spiSettings.dataMode, + _spiSettings.bitOrder, _spiSettings.deviceMode); } /** diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index a558f5f05c..07a42134bb 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -43,27 +43,31 @@ extern "C" { class SPISettings { public: - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, SPIDeviceMode deviceMode = SPI_MASTER) : clockFreq(clock), bitOrder(bitOrder), - dataMode((SPIMode)dataMode) + dataMode((SPIMode)dataMode), + deviceMode(deviceMode) { } - constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode) + constexpr SPISettings(uint32_t clock, BitOrder bitOrder, SPIMode dataMode, SPIDeviceMode deviceMode = SPI_MASTER) : clockFreq(clock), bitOrder(bitOrder), - dataMode(dataMode) + dataMode(dataMode), + deviceMode(deviceMode) { } constexpr SPISettings() : clockFreq(SPI_SPEED_CLOCK_DEFAULT), bitOrder(MSBFIRST), - dataMode(SPI_MODE0) + dataMode(SPI_MODE0), + deviceMode(SPI_MASTER) { } bool operator==(const SPISettings &rhs) const { if ((this->clockFreq == rhs.clockFreq) && (this->bitOrder == rhs.bitOrder) && - (this->dataMode == rhs.dataMode)) { + (this->dataMode == rhs.dataMode) && + (this->deviceMode == rhs.deviceMode)) { return true; } return false; @@ -75,9 +79,10 @@ class SPISettings { } private: - uint32_t clockFreq; //specifies the spi bus maximum clock speed - BitOrder bitOrder; //bit order (MSBFirst or LSBFirst) - SPIMode dataMode; //one of the data mode + uint32_t clockFreq; // specifies the spi bus maximum clock speed + BitOrder bitOrder; // bit order (MSBFirst or LSBFirst) + SPIMode dataMode; // one of the data mode + SPIDeviceMode deviceMode; // device mode: master or slave friend class SPIClass; }; @@ -121,7 +126,7 @@ class SPIClass { _spi.pin_ssel = (ssel); }; - void begin(void); + void begin(SPIDeviceMode device = SPI_MASTER); void end(void); /* This function should be used to configure the SPI instance in case you @@ -162,6 +167,17 @@ class SPIClass { return &(_spi.handle); } + // Dedicated to SPI Slave + void attachSlaveInterrupt(uint8_t pin, callback_function_t callback) + { + ::attachInterrupt(pin, callback, FALLING); + } + + void detachSlaveInterrupt(uint8_t pin) + { + ::detachInterrupt(pin); + } + protected: // spi instance spi_t _spi; diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index 8bdb56f303..58da63ee02 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -29,8 +29,9 @@ extern "C" { uint32_t spi_getClkFreqInst(SPI_TypeDef *spi_inst) { uint32_t spi_freq = SystemCoreClock; -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) (void)spi_inst; // Avoid unused parameter warning + spi_freq = SystemCoreClock / 4; #else if (spi_inst != NP) { #if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || \ @@ -203,9 +204,10 @@ static uint32_t compute_disable_delay(spi_t *obj) * @param speed : spi output speed * @param mode : one of the spi modes * @param msb : set to 1 in msb first + * @param device : spi device mode: master or slave * @retval None */ -void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb, SPIDeviceMode device) { if (obj == NULL) { return; @@ -257,8 +259,8 @@ void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb) } /* Fill default value */ - handle->Instance = obj->spi; - handle->Init.Mode = SPI_MODE_MASTER; + handle->Instance = obj->spi; + handle->Init.Mode = (device == SPI_MASTER) ? SPI_MODE_MASTER : SPI_MODE_SLAVE; spi_freq = spi_getClkFreqInst(obj->spi); /* For SUBGHZSPI, 'SPI_BAUDRATEPRESCALER_*' == 'SUBGHZSPI_BAUDRATEPRESCALER_*' */ diff --git a/libraries/SPI/src/utility/spi_com.h b/libraries/SPI/src/utility/spi_com.h index 4d145ff7fd..cdde9ed0d2 100644 --- a/libraries/SPI/src/utility/spi_com.h +++ b/libraries/SPI/src/utility/spi_com.h @@ -74,6 +74,12 @@ typedef enum { SPI_MODE3 = 3, } SPIMode; +// Device mode +typedef enum { + SPI_MASTER, /* Device is master */ + SPI_SLAVE /* Device is slave */ +} SPIDeviceMode; + ///@brief SPI errors typedef enum { SPI_OK = 0, @@ -82,7 +88,7 @@ typedef enum { } spi_status_e; /* Exported functions ------------------------------------------------------- */ -void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb); +void spi_init(spi_t *obj, uint32_t speed, SPIMode mode, uint8_t msb, SPIDeviceMode device); void spi_deinit(spi_t *obj); spi_status_e spi_transfer(spi_t *obj, const uint8_t *tx_buffer, uint8_t *rx_buffer, uint16_t len); uint32_t spi_getClkFreq(spi_t *obj); diff --git a/libraries/SrcWrapper/CMakeLists.txt b/libraries/SrcWrapper/CMakeLists.txt index b1ab237e09..ea4dacda44 100644 --- a/libraries/SrcWrapper/CMakeLists.txt +++ b/libraries/SrcWrapper/CMakeLists.txt @@ -80,6 +80,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_iwdg.c src/HAL/stm32yyxx_hal_jpeg.c src/HAL/stm32yyxx_hal_lcd.c + src/HAL/stm32yyxx_hal_lpawur.c src/HAL/stm32yyxx_hal_lptim.c src/HAL/stm32yyxx_hal_ltdc.c src/HAL/stm32yyxx_hal_ltdc_ex.c @@ -88,6 +89,8 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_mdma.c src/HAL/stm32yyxx_hal_mmc.c src/HAL/stm32yyxx_hal_mmc_ex.c + src/HAL/stm32yyxx_hal_mrsubg.c + src/HAL/stm32yyxx_hal_mrsubg_timer.c src/HAL/stm32yyxx_hal_nand.c src/HAL/stm32yyxx_hal_nor.c src/HAL/stm32yyxx_hal_opamp.c @@ -160,6 +163,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/LL/stm32yyxx_ll_i2c.c src/LL/stm32yyxx_ll_i3c.c src/LL/stm32yyxx_ll_icache.c + src/LL/stm32yyxx_ll_lcsc.c src/LL/stm32yyxx_ll_lpgpio.c src/LL/stm32yyxx_ll_lptim.c src/LL/stm32yyxx_ll_lpuart.c diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h index aafced07af..da0ba55042 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll.h @@ -37,10 +37,14 @@ #include "stm32yyxx_ll_icache.h" #include "stm32yyxx_ll_ipcc.h" #include "stm32yyxx_ll_iwdg.h" +#include "stm32yyxx_ll_lcsc.h" +#include "stm32yyxx_ll_lpawur.h" #include "stm32yyxx_ll_lpgpio.h" #include "stm32yyxx_ll_lptim.h" #include "stm32yyxx_ll_lpuart.h" #include "stm32yyxx_ll_mdma.h" +#include "stm32yyxx_ll_mrsubg.h" +#include "stm32yyxx_ll_mrsubg_timer.h" #include "stm32yyxx_ll_opamp.h" #include "stm32yyxx_ll_pka.h" #include "stm32yyxx_ll_pwr.h" diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h index f5d0b14996..42ea7d18ec 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_adc.h" #elif STM32WLxx #include "stm32wlxx_ll_adc.h" +#elif STM32WL3x + #include "stm32wl3x_ll_adc.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_ADC_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h index 9a3aa4007f..f8d0641690 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_bus.h" #elif STM32WLxx #include "stm32wlxx_ll_bus.h" +#elif STM32WL3x + #include "stm32wl3x_ll_bus.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_BUS_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h index f9a97cdce2..d65e144376 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h @@ -40,6 +40,8 @@ #include "stm32wbaxx_ll_comp.h" #elif STM32WLxx #include "stm32wlxx_ll_comp.h" +#elif STM32WL3x + #include "stm32wl3x_ll_comp.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_COMP_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h index baa033f29b..3ec27ebcd2 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_cortex.h" #elif STM32WLxx #include "stm32wlxx_ll_cortex.h" +#elif STM32WL3x + #include "stm32wl3x_ll_cortex.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_CORTEX_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h index 3e5dc3a451..2682fdefa1 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h @@ -52,6 +52,8 @@ #include "stm32wbaxx_ll_crc.h" #elif STM32WLxx #include "stm32wlxx_ll_crc.h" +#elif STM32WL3x + #include "stm32wl3x_ll_crc.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_CRC_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h index ef0f921d37..57368f1f55 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_dac.h" #elif STM32WLxx #include "stm32wlxx_ll_dac.h" +#elif STM32WL3x + #include "stm32wl3x_ll_dac.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_DAC_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h index 9e7790b1da..e67dd70811 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_dma.h" #elif STM32WLxx #include "stm32wlxx_ll_dma.h" +#elif STM32WL3x + #include "stm32wl3x_ll_dma.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_DMA_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h index 2cef22496d..6521d96b42 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h @@ -30,6 +30,8 @@ #include "stm32wb0x_ll_dmamux.h" #elif STM32WLxx #include "stm32wlxx_ll_dmamux.h" +#elif STM32WL3x + #include "stm32wl3x_ll_dmamux.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_DMAMUX_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h index 0adb4d45a9..4091089b0f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_gpio.h" #elif STM32WLxx #include "stm32wlxx_ll_gpio.h" +#elif STM32WL3x + #include "stm32wl3x_ll_gpio.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_GPIO_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h index fb231bdc95..21cca702b7 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_i2c.h" #elif STM32WLxx #include "stm32wlxx_ll_i2c.h" +#elif STM32WL3x + #include "stm32wl3x_ll_i2c.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_I2C_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h index 287be5e777..f00c148b86 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h @@ -52,6 +52,8 @@ #include "stm32wbaxx_ll_iwdg.h" #elif STM32WLxx #include "stm32wlxx_ll_iwdg.h" +#elif STM32WL3x + #include "stm32wl3x_ll_iwdg.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_IWDG_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lcsc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lcsc.h new file mode 100644 index 0000000000..d3b36d1cda --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lcsc.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_LCSC_H_ +#define _STM32YYXX_LL_LCSC_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32WL3x + #include "stm32wl3x_ll_lcsc.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_LCSC_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpawur.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpawur.h new file mode 100644 index 0000000000..30f2763d5e --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpawur.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_LPAWUR_H_ +#define _STM32YYXX_LL_LPAWUR_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32WL3x + #include "stm32wl3x_ll_lpawur.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_LPAWUR_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h index b41d89210d..36bae145b4 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h @@ -36,6 +36,8 @@ #include "stm32wbaxx_ll_lpuart.h" #elif STM32WLxx #include "stm32wlxx_ll_lpuart.h" +#elif STM32WL3x + #include "stm32wl3x_ll_lpuart.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_LPUART_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_mrsubg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_mrsubg.h new file mode 100644 index 0000000000..6b7c095028 --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_mrsubg.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_MRSUBG_H_ +#define _STM32YYXX_LL_MRSUBG_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32WL3x + #include "stm32wl3x_ll_mrsubg.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_MRSUBG_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_mrsubg_timer.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_mrsubg_timer.h new file mode 100644 index 0000000000..7491d7c161 --- /dev/null +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_mrsubg_timer.h @@ -0,0 +1,15 @@ +#ifndef _STM32YYXX_LL_MRSUBG_TIMER_H_ +#define _STM32YYXX_LL_MRSUBG_TIMER_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#ifdef __cplusplus + #pragma GCC diagnostic ignored "-Wregister" +#endif + +#ifdef STM32WL3x + #include "stm32wl3x_ll_mrsubg_timer.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_MRSUBG_TIMER_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h index 53adf05edf..7497fee559 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_pwr.h" #elif STM32WLxx #include "stm32wlxx_ll_pwr.h" +#elif STM32WL3x + #include "stm32wl3x_ll_pwr.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_PWR_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_timer.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_radio_timer.h similarity index 65% rename from libraries/SrcWrapper/inc/LL/stm32yyxx_ll_timer.h rename to libraries/SrcWrapper/inc/LL/stm32yyxx_ll_radio_timer.h index 9fbb78f288..b8875b6d2a 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_timer.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_radio_timer.h @@ -1,5 +1,5 @@ -#ifndef _STM32YYXX_LL_TIMER_H_ -#define _STM32YYXX_LL_TIMER_H_ +#ifndef _STM32YYXX_LL_RADIO_TIMER_H_ +#define _STM32YYXX_LL_RADIO_TIMER_H_ /* LL raised several warnings, ignore them */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" @@ -9,7 +9,7 @@ #endif #ifdef STM32WB0x - #include "stm32wb0x_ll_timer.h" + #include "stm32wb0x_ll_radio_timer.h" #endif #pragma GCC diagnostic pop -#endif /* _STM32YYXX_LL_TIMER_H_ */ +#endif /* _STM32YYXX_LL_RADIO_TIMER_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h index e5a7fdc5d3..76da68c77f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_rcc.h" #elif STM32WLxx #include "stm32wlxx_ll_rcc.h" +#elif STM32WL3x + #include "stm32wl3x_ll_rcc.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_RCC_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h index beb5a749b8..2ec687c69b 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h @@ -42,6 +42,8 @@ #include "stm32wbaxx_ll_rng.h" #elif STM32WLxx #include "stm32wlxx_ll_rng.h" +#elif STM32WL3x + #include "stm32wl3x_ll_rng.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_RNG_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h index 80a1d71cfa..c98336ddee 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_rtc.h" #elif STM32WLxx #include "stm32wlxx_ll_rtc.h" +#elif STM32WL3x + #include "stm32wl3x_ll_rtc.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_RTC_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h index d6fe1411ba..3c8c43f07a 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_spi.h" #elif STM32WLxx #include "stm32wlxx_ll_spi.h" +#elif STM32WL3x + #include "stm32wl3x_ll_spi.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_SPI_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h index 78b7e0aab8..3b71e3c082 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_system.h" #elif STM32WLxx #include "stm32wlxx_ll_system.h" +#elif STM32WL3x + #include "stm32wl3x_ll_system.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_SYSTEM_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h index 074ba40b7b..55fd9924cc 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_tim.h" #elif STM32WLxx #include "stm32wlxx_ll_tim.h" +#elif STM32WL3x + #include "stm32wl3x_ll_tim.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_TIM_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h index 870bef4fa6..4982dd5faa 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_usart.h" #elif STM32WLxx #include "stm32wlxx_ll_usart.h" +#elif STM32WL3x + #include "stm32wl3x_ll_usart.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_USART_H_ */ diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h index 515c4827ac..f75f9f96fb 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h @@ -54,6 +54,8 @@ #include "stm32wbaxx_ll_utils.h" #elif STM32WLxx #include "stm32wlxx_ll_utils.h" +#elif STM32WL3x + #include "stm32wl3x_ll_utils.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_UTILS_H_ */ diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index fabc06919b..6c96a7be6d 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -6,7 +6,7 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x0BU) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_MINOR (0x0CU) /*!< [23:16] minor version */ #define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: @@ -14,7 +14,7 @@ * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ @@ -64,6 +64,8 @@ #include "stm32wbxx.h" #elif defined(STM32WBAxx) #include "stm32wbaxx.h" +#elif defined(STM32WL3x) + #include "stm32wl3x.h" #elif defined(STM32WLxx) #include "stm32wlxx.h" #else @@ -220,9 +222,14 @@ __STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU #define GPIO_AF1_SPI1 STM_PIN_AFNUM_MASK #endif -#if defined(STM32C0xx) && defined(USART3) && !defined(GPIO_AF7_USART3) - #define GPIO_AF7_USART3 ((uint8_t)0x07) -#endif // STM32C0xx && !defined(USART3) +#if defined(STM32C0xx) + #if defined(USART3) && !defined(GPIO_AF7_USART3) + #define GPIO_AF7_USART3 ((uint8_t)0x07) + #endif /* USART3 & !GPIO_AF7_USART3*/ + #if defined(STM32C051xx) && !defined(GPIO_AF0_USART2) + #define GPIO_AF0_USART2 ((uint8_t)0x00) + #endif +#endif // STM32C0xx #if defined(STM32WBAxx) && defined(USB_OTG_HS) && !defined(GPIO_AF4_USB_OTG_HS) #define GPIO_AF4_USB_OTG_HS GPIO_AF4_OTG_HS diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h index 6c466ebe8c..c3a330820c 100644 --- a/libraries/SrcWrapper/inc/uart.h +++ b/libraries/SrcWrapper/inc/uart.h @@ -272,6 +272,11 @@ void uart_enable_rx(serial_t *obj); size_t uart_debug_write(uint8_t *data, uint32_t size); +#if defined(UART_PRESCALER_DIV1) +uint32_t uart_compute_prescaler(UART_HandleTypeDef *huart); +uint32_t uart_get_clock_source_freq(UART_HandleTypeDef *huart); +#endif + #endif /* HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY */ #ifdef __cplusplus } diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c index a74f6a4e5d..7fe8ee664d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c @@ -52,5 +52,7 @@ #include "stm32wbaxx_hal.c" #elif STM32WLxx #include "stm32wlxx_hal.c" +#elif STM32WL3x + #include "stm32wl3x_hal.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c index 56b3e1771f..fdbc8577c8 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_adc.c" #elif STM32WLxx #include "stm32wlxx_hal_adc.c" +#elif STM32WL3x + #include "stm32wl3x_hal_adc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c index 7122dac222..16a9351af8 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c @@ -34,5 +34,7 @@ #include "stm32wbaxx_hal_comp.c" #elif STM32WLxx #include "stm32wlxx_hal_comp.c" +#elif STM32WL3x + #include "stm32wl3x_hal_comp.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c index 3fbe9116d1..1123b90339 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_cortex.c" #elif STM32WLxx #include "stm32wlxx_hal_cortex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_cortex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c index af8450a6f0..5c05b31859 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_crc.c" #elif STM32WLxx #include "stm32wlxx_hal_crc.c" +#elif STM32WL3x + #include "stm32wl3x_hal_crc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c index fcbef4c773..ac35096a51 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c @@ -40,5 +40,7 @@ #include "stm32wbaxx_hal_crc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_crc_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_crc_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c index a444fc0a32..a2ce1877f2 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c @@ -38,5 +38,7 @@ #include "stm32wbaxx_hal_cryp.c" #elif STM32WLxx #include "stm32wlxx_hal_cryp.c" +#elif STM32WL3x + #include "stm32wl3x_hal_cryp.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c index 136ed44bf1..90f7d130eb 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c @@ -36,5 +36,7 @@ #include "stm32wbaxx_hal_cryp_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_cryp_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_cryp_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c index b1007e8347..c974411a98 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c @@ -40,5 +40,7 @@ #include "stm32u5xx_hal_dac.c" #elif STM32WLxx #include "stm32wlxx_hal_dac.c" +#elif STM32WL3x + #include "stm32wl3x_hal_dac.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c index 30c7b6c1e0..d0f6f96df5 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c @@ -40,5 +40,7 @@ #include "stm32u5xx_hal_dac_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_dac_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_dac_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c index abae861864..84ee04d2f1 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_dma.c" #elif STM32WLxx #include "stm32wlxx_hal_dma.c" +#elif STM32WL3x + #include "stm32wl3x_hal_dma.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c index 1fb6939cdb..4aa59d41b7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c @@ -46,5 +46,7 @@ #include "stm32wbaxx_hal_flash.c" #elif STM32WLxx #include "stm32wlxx_hal_flash.c" +#elif STM32WL3x + #include "stm32wl3x_hal_flash.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c index 41d00166e3..a7975f49be 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c @@ -46,5 +46,7 @@ #include "stm32wbaxx_hal_flash_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_flash_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_flash_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c index 6a852e8f53..65c745ba0a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_gpio.c" #elif STM32WLxx #include "stm32wlxx_hal_gpio.c" +#elif STM32WL3x + #include "stm32wl3x_hal_gpio.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c index 7c82a3e913..86ceb664d0 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_i2c.c" #elif STM32WLxx #include "stm32wlxx_hal_i2c.c" +#elif STM32WL3x + #include "stm32wl3x_hal_i2c.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c index 4603cab322..bf01bcb44a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c @@ -42,5 +42,7 @@ #include "stm32wbaxx_hal_i2c_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_i2c_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_i2c_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c index 32d5f7e8e0..edd771efb7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2s.c @@ -32,5 +32,7 @@ #include "stm32wb0x_hal_i2s.c" #elif STM32WLxx #include "stm32wlxx_hal_i2s.c" +#elif STM32WL3x + #include "stm32wl3x_hal_i2s.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c index c4a66e19ed..b91abe17cb 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c @@ -46,5 +46,7 @@ #include "stm32wbaxx_hal_irda.c" #elif STM32WLxx #include "stm32wlxx_hal_irda.c" +#elif STM32WL3x + #include "stm32wl3x_hal_irda.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c index 879329769f..43dde13f6b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c @@ -46,5 +46,7 @@ #include "stm32wbaxx_hal_iwdg.c" #elif STM32WLxx #include "stm32wlxx_hal_iwdg.c" +#elif STM32WL3x + #include "stm32wl3x_hal_iwdg.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c index 2f48bd72d8..34dc969921 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c @@ -12,5 +12,7 @@ #include "stm32u0xx_hal_lcd.c" #elif STM32WBxx #include "stm32wbxx_hal_lcd.c" +#elif STM32WL3x + #include "stm32wl3x_hal_lcd.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lpawur.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lpawur.c new file mode 100644 index 0000000000..b7403567bd --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lpawur.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32WL3x + #include "stm32wl3x_hal_lpawur.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_mrsubg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_mrsubg.c new file mode 100644 index 0000000000..d2b4a8398b --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_mrsubg.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32WL3x + #include "stm32wl3x_hal_mrsubg.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_mrsubg_timer.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_mrsubg_timer.c new file mode 100644 index 0000000000..ae7098cd5a --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_mrsubg_timer.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32WL3x + #include "stm32wl3x_hal_mrsubg_timer.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c index c95b5e4f3f..7ceda97c6a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_pwr.c" #elif STM32WLxx #include "stm32wlxx_hal_pwr.c" +#elif STM32WL3x + #include "stm32wl3x_hal_pwr.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c index 07c296b167..21d4214d0c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c @@ -46,5 +46,7 @@ #include "stm32wbaxx_hal_pwr_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_pwr_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_pwr_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c index ca1cce8a18..bcfcc12566 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_rcc.c" #elif STM32WLxx #include "stm32wlxx_hal_rcc.c" +#elif STM32WL3x + #include "stm32wl3x_hal_rcc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c index c610421e8f..8897cb47ba 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_rcc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_rcc_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_rcc_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c index 5b3dbb5b7e..cd5871929c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c @@ -38,5 +38,7 @@ #include "stm32wbaxx_hal_rng.c" #elif STM32WLxx #include "stm32wlxx_hal_rng.c" +#elif STM32WL3x + #include "stm32wl3x_hal_rng.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c index c8d5205f97..b0e0d84f0b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_rtc.c" #elif STM32WLxx #include "stm32wlxx_hal_rtc.c" +#elif STM32WL3x + #include "stm32wl3x_hal_rtc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c index 14aeabb53d..5c9c549e34 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_rtc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_rtc_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_rtc_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c index 5e705f55ed..0f9b8774f7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_smartcard.c" #elif STM32WLxx #include "stm32wlxx_hal_smartcard.c" +#elif STM32WL3x + #include "stm32wl3x_hal_smartcard.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c index cc803f2d22..101c060e23 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c @@ -40,5 +40,7 @@ #include "stm32wbaxx_hal_smartcard_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_smartcard_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_smartcard_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c index b9f5c6bf28..92b386514a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c @@ -42,5 +42,7 @@ #include "stm32wbaxx_hal_smbus.c" #elif STM32WLxx #include "stm32wlxx_hal_smbus.c" +#elif STM32WL3x + #include "stm32wl3x_hal_smbus.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c index e9b4ffbe1c..16b396019c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c @@ -32,5 +32,7 @@ #include "stm32wbaxx_hal_smbus_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_smbus_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_smbus_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c index ea979c0e51..32e26f3855 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_spi.c" #elif STM32WLxx #include "stm32wlxx_hal_spi.c" +#elif STM32WL3x + #include "stm32wl3x_hal_spi.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c index d237ea6173..c73c522ab1 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c @@ -38,5 +38,7 @@ #include "stm32wbaxx_hal_spi_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_spi_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_spi_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c index 29e226289e..16642e5d39 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_tim.c" #elif STM32WLxx #include "stm32wlxx_hal_tim.c" +#elif STM32WL3x + #include "stm32wl3x_hal_tim.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c index 503ac3a9bd..421414a0ea 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_tim_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_tim_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_tim_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c index 1ff1b18ca4..bf975c9cfa 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_uart.c" #elif STM32WLxx #include "stm32wlxx_hal_uart.c" +#elif STM32WL3x + #include "stm32wl3x_hal_uart.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c index d1d21c32ac..eb76a018ab 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c @@ -40,5 +40,7 @@ #include "stm32wbaxx_hal_uart_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_uart_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_uart_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c index ffc548a8a7..90d1d9f7c2 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_hal_usart.c" #elif STM32WLxx #include "stm32wlxx_hal_usart.c" +#elif STM32WL3x + #include "stm32wl3x_hal_usart.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c index f887f1c98e..1a700fd384 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c @@ -36,5 +36,7 @@ #include "stm32wbaxx_hal_usart_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_usart_ex.c" +#elif STM32WL3x + #include "stm32wl3x_hal_usart_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HardwareTimer.cpp b/libraries/SrcWrapper/src/HardwareTimer.cpp index 552b8f78df..35fed3f7b4 100644 --- a/libraries/SrcWrapper/src/HardwareTimer.cpp +++ b/libraries/SrcWrapper/src/HardwareTimer.cpp @@ -281,16 +281,20 @@ uint32_t HardwareTimer::getLLChannel(uint32_t channel) case 1: ll_channel = LL_TIM_CHANNEL_CH1N; break; +#if defined(TIM_CCER_CC2NE) #if defined(LL_TIM_CHANNEL_CH2N) case 2: ll_channel = LL_TIM_CHANNEL_CH2N; break; #endif +#endif +#if defined(TIM_CCER_CC3NE) #if defined(LL_TIM_CHANNEL_CH3N) case 3: ll_channel = LL_TIM_CHANNEL_CH3N; break; #endif +#endif #if defined(LL_TIM_CHANNEL_CH4N) case 4: ll_channel = LL_TIM_CHANNEL_CH4N; @@ -1347,7 +1351,7 @@ uint32_t HardwareTimer::getTimerClkFreq() uint8_t timerClkSrc = getTimerClkSrc(_timerObj.handle.Instance); uint64_t clkSelection = timerClkSrc == 1 ? RCC_PERIPHCLK_TIMG1 : RCC_PERIPHCLK_TIMG2; return HAL_RCCEx_GetPeriphCLKFreq(clkSelection); -#elif defined(STM32WB0x) +#elif defined(STM32WB0x) || defined(STM32WL3x) return SystemCoreClock; #else RCC_ClkInitTypeDef clkconfig = {}; diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c index 3b2a03899b..cedcf42f83 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_adc.c" #elif STM32WLxx #include "stm32wlxx_ll_adc.c" +#elif STM32WL3x + #include "stm32wl3x_ll_adc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c index c0896e5c29..19da985976 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c @@ -34,5 +34,7 @@ #include "stm32wbaxx_ll_comp.c" #elif STM32WLxx #include "stm32wlxx_ll_comp.c" +#elif STM32WL3x + #include "stm32wl3x_ll_comp.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c index 7c6e744c95..23728654ff 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c @@ -46,5 +46,7 @@ #include "stm32wbaxx_ll_crc.c" #elif STM32WLxx #include "stm32wlxx_ll_crc.c" +#elif STM32WL3x + #include "stm32wl3x_ll_crc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c index 871641da7f..9da5894ac3 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c @@ -38,5 +38,7 @@ #include "stm32u5xx_ll_dac.c" #elif STM32WLxx #include "stm32wlxx_ll_dac.c" +#elif STM32WL3x + #include "stm32wl3x_ll_dac.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c index a4e20870af..c26e5eaa47 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_dma.c" #elif STM32WLxx #include "stm32wlxx_ll_dma.c" +#elif STM32WL3x + #include "stm32wl3x_ll_dma.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c index c85aecc17e..3ce93a645f 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_gpio.c" #elif STM32WLxx #include "stm32wlxx_ll_gpio.c" +#elif STM32WL3x + #include "stm32wl3x_ll_gpio.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c index 8a6e9c5a7d..13571e2e6d 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_i2c.c" #elif STM32WLxx #include "stm32wlxx_ll_i2c.c" +#elif STM32WL3x + #include "stm32wl3x_ll_i2c.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lcsc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lcsc.c new file mode 100644 index 0000000000..abf3e2796b --- /dev/null +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lcsc.c @@ -0,0 +1,8 @@ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32WL3x + #include "stm32wl3x_ll_lcsc.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c index eb47270483..9daa960f61 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c @@ -30,5 +30,7 @@ #include "stm32wbaxx_ll_lpuart.c" #elif STM32WLxx #include "stm32wlxx_ll_lpuart.c" +#elif STM32WL3x + #include "stm32wl3x_ll_lpuart.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c index ee1de61649..2e520ed345 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_pwr.c" #elif STM32WLxx #include "stm32wlxx_ll_pwr.c" +#elif STM32WL3x + #include "stm32wl3x_ll_pwr.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c index 0f46b1d9d2..d054c74b9c 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_rcc.c" #elif STM32WLxx #include "stm32wlxx_ll_rcc.c" +#elif STM32WL3x + #include "stm32wl3x_ll_rcc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c index a7ad1ac92c..8a21e704d0 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c @@ -36,5 +36,7 @@ #include "stm32wbaxx_ll_rng.c" #elif STM32WLxx #include "stm32wlxx_ll_rng.c" +#elif STM32WL3x + #include "stm32wl3x_ll_rng.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c index 573f24849c..44a5d66275 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_rtc.c" #elif STM32WLxx #include "stm32wlxx_ll_rtc.c" +#elif STM32WL3x + #include "stm32wl3x_ll_rtc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c index 2029508a21..801f235a32 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_spi.c" #elif STM32WLxx #include "stm32wlxx_ll_spi.c" +#elif STM32WL3x + #include "stm32wl3x_ll_spi.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_system.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_system.c index 8e7fed5fc4..bab6f73882 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_system.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_system.c @@ -4,5 +4,7 @@ #ifdef STM32WB0x #include "stm32wb0x_ll_system.c" +#elif STM32WL3x + #include "stm32wl3x_ll_system.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c index 99079ee822..685b2b49b5 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_tim.c" #elif STM32WLxx #include "stm32wlxx_ll_tim.c" +#elif STM32WL3x + #include "stm32wl3x_ll_tim.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c index 7a9d6a0e91..df93b37dbf 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_usart.c" #elif STM32WLxx #include "stm32wlxx_ll_usart.c" +#elif STM32WL3x + #include "stm32wl3x_ll_usart.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c index fdd3fbedbd..8666f91831 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c @@ -48,5 +48,7 @@ #include "stm32wbaxx_ll_utils.c" #elif STM32WLxx #include "stm32wlxx_ll_utils.c" +#elif STM32WL3x + #include "stm32wl3x_ll_utils.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 0d34a4f4d3..98c17eafd3 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -30,7 +30,7 @@ static PinName g_current_pin = NC; /* Private_Defines */ #if defined(HAL_ADC_MODULE_ENABLED) && !defined(HAL_ADC_MODULE_ONLY) -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) #ifndef ADC_SAMPLING_RATE #define ADC_SAMPLING_RATE ADC_SAMPLE_RATE_16 #endif /* !ADC_SAMPLING_RATE */ @@ -117,7 +117,7 @@ static PinName g_current_pin = NC; #ifndef ADC_REGULAR_RANK_1 #define ADC_REGULAR_RANK_1 1 #endif -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ /* Exported Functions */ /** @@ -474,7 +474,11 @@ void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) } /*##-3- Set DAC Channel1 DHR register ######################################*/ +#if defined(DAC_ALIGN_12B_R) if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_12B_R, value) != HAL_OK) { +#else + if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_6B_R, value) != HAL_OK) { +#endif /* Setting value Error */ return; } @@ -843,12 +847,12 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) ADC_HandleTypeDef AdcHandle = {}; ADC_ChannelConfTypeDef AdcChannelConf = {}; __IO uint16_t uhADCxConvertedValue = 0; -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) uint32_t samplingRate = ADC_SAMPLING_RATE; uint32_t voltageRange = ADC_VOLT_RANGE; #else uint32_t samplingTime = ADC_SAMPLINGTIME; -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ uint32_t channel = 0; uint32_t bank = 0; @@ -870,7 +874,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif #endif channel = get_adc_internal_channel(pin); -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) samplingRate = ADC_SAMPLING_RATE_INTERNAL; if (channel == ADC_CHANNEL_TEMPSENSOR) { voltageRange = ADC_VIN_RANGE_1V2; @@ -879,13 +883,11 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) } #else samplingTime = ADC_SAMPLINGTIME_INTERNAL; -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ } else { AdcHandle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); channel = get_adc_channel(pin, &bank); -#if defined(STM32WB0x) - -#else +#if !defined(STM32WB0x) && !defined(STM32WL3x) #if defined(ADC_VER_V5_V90) if (AdcHandle.Instance == ADC3) { samplingTime = ADC3_SAMPLINGTIME; @@ -896,14 +898,16 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) samplingTime = ADC4_SAMPLINGTIME; } #endif -#endif /* STM32WB0x */ +#endif /* !STM32WB0x && !STM32WL3x */ } if (AdcHandle.Instance == NP) { return 0; } -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) +#if defined(ADC_CONVERSION_WITH_DS) AdcHandle.Init.ConversionType = ADC_CONVERSION_WITH_DS; +#endif /* ADC_CONVERSION_WITH_DS */ AdcHandle.Init.ContinuousConvMode = DISABLE; AdcHandle.Init.SequenceLength = 1; AdcHandle.Init.SamplingMode = ADC_SAMPLING_AT_START; @@ -1047,7 +1051,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #ifdef ADC_VREF_PPROT_NONE AdcHandle.Init.VrefProtection = ADC_VREF_PPROT_NONE; #endif -#endif /* STM32WB0x*/ +#endif /* STM32WB0x || STM32WL3x */ AdcHandle.State = HAL_ADC_STATE_RESET; AdcHandle.DMA_Handle = NULL; AdcHandle.Lock = HAL_UNLOCKED; @@ -1070,7 +1074,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) return 0; } -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) AdcChannelConf.Rank = ADC_RANK_1; AdcChannelConf.VoltRange = voltageRange; AdcChannelConf.CalibrationPoint.Number = ADC_CALIB_POINT_1; @@ -1138,7 +1142,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) AdcChannelConf.OffsetRightShift = DISABLE; /* No Right Offset Shift */ AdcChannelConf.OffsetSignedSaturation = DISABLE; /* Signed saturation feature is not used */ #endif -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ /*##-2- Configure ADC regular channel ######################################*/ if (HAL_ADC_ConfigChannel(&AdcHandle, &AdcChannelConf) != HAL_OK) { /* Channel Configuration Error */ diff --git a/libraries/SrcWrapper/src/stm32/clock.c b/libraries/SrcWrapper/src/stm32/clock.c index 6c12eccea5..2498583348 100644 --- a/libraries/SrcWrapper/src/stm32/clock.c +++ b/libraries/SrcWrapper/src/stm32/clock.c @@ -130,7 +130,7 @@ void enableClock(sourceClock_t source) if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; -#if !defined(STM32WB0x) +#if !defined(STM32WB0x) && !defined(STM32WL3x) #if defined(STM32MP1xx) RCC_OscInitStruct.HSICalibrationValue = 0x00; #else diff --git a/libraries/SrcWrapper/src/stm32/interrupt.cpp b/libraries/SrcWrapper/src/stm32/interrupt.cpp index 2872941994..31bc13771d 100644 --- a/libraries/SrcWrapper/src/stm32/interrupt.cpp +++ b/libraries/SrcWrapper/src/stm32/interrupt.cpp @@ -43,7 +43,7 @@ #if !defined(HAL_EXTI_MODULE_DISABLED) /* Private Types */ -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) static std::function gpio_callback[2][16] = { { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -129,7 +129,7 @@ static const uint32_t ll_exti_lines[NB_EXTI] = { LL_EXTI_LINE_8, LL_EXTI_LINE_9, LL_EXTI_LINE_10, LL_EXTI_LINE_11, LL_EXTI_LINE_12, LL_EXTI_LINE_13, LL_EXTI_LINE_14, LL_EXTI_LINE_15 }; -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ /* Private Functions */ /** * @brief This function returns the pin ID function of the HAL PIN definition @@ -165,7 +165,7 @@ void stm32_interrupt_enable(PinName pn, callback_function_t callback, uint32_t m hsem_unlock(CFG_HW_GPIO_SEMID); } IRQn_Type irqnb; -#ifdef STM32WB0x +#if defined(STM32WB0x) || defined(STM32WL3x) if (port == GPIOA) { irqnb = GPIOA_IRQn; gpio_callback[0][id] = callback; @@ -176,7 +176,7 @@ void stm32_interrupt_enable(PinName pn, callback_function_t callback, uint32_t m #else gpio_irq_conf[id].callback = callback; irqnb = gpio_irq_conf[id].irqnb; -#endif /* STM32WB0x */ +#endif /* STM32WB0x || */ // Enable and set EXTI Interrupt HAL_NVIC_SetPriority(irqnb, EXTI_IRQ_PRIO, EXTI_IRQ_SUBPRIO); HAL_NVIC_EnableIRQ(irqnb); @@ -208,7 +208,7 @@ void stm32_interrupt_disable(GPIO_TypeDef *port, uint16_t pin) { UNUSED(port); uint8_t id = get_pin_id(pin); -#ifdef STM32WB0x +#if defined(STM32WB0x) || defined(STM32WL3x) uint8_t pid = 0; IRQn_Type irqnb; if (port == GPIOA) { @@ -236,11 +236,11 @@ void stm32_interrupt_disable(GPIO_TypeDef *port, uint16_t pin) } LL_EXTI_DisableIT_0_31(ll_exti_lines[id]); HAL_NVIC_DisableIRQ(gpio_irq_conf[id].irqnb); -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ } -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) #ifdef __cplusplus extern "C" { #endif @@ -560,7 +560,7 @@ void EXTI15_IRQHandler(void) #ifdef __cplusplus } #endif -#endif /* !STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ #endif /* !HAL_EXTI_MODULE_DISABLED */ #endif diff --git a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c index 79425e068a..570b3417e2 100644 --- a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c +++ b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c @@ -42,6 +42,8 @@ #include "system_stm32wbaxx.c" #elif STM32WBxx #include "system_stm32wbxx.c" +#elif STM32WL3x + #include "system_stm32wl3x.c" #elif STM32WLxx #include "system_stm32wlxx.c" #endif diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index db791c94f4..27ffd9fbee 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -413,6 +413,18 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par huart->Init.Mode = UART_MODE_TX_RX; huart->Init.HwFlowCtl = flow_control; huart->Init.OverSampling = UART_OVERSAMPLING_16; + + /* Configure UART Clock Prescaler */ +#if defined(UART_PRESCALER_DIV1) + huart->Init.ClockPrescaler = uart_compute_prescaler(huart); + if (!IS_UART_PRESCALER(huart->Init.ClockPrescaler)) { + if (obj != &serial_debug) { + core_debug("WARNING: [U(S)ART] wrong prescaler, reset to UART_PRESCALER_DIV1!\n"); + } + huart->Init.ClockPrescaler = UART_PRESCALER_DIV1; + } +#endif + #if defined(UART_ADVFEATURE_NO_INIT) // Default value huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; @@ -1415,6 +1427,144 @@ void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) serial_t *obj = get_serial_obj(huart); HAL_UART_Receive_IT(huart, &(obj->recv), 1); } + +/** + * @brief Function called to set the uart clock prescaler + * @param huart : uart handle structure + * @retval uint32_t clock prescaler + */ +#if defined(UART_PRESCALER_DIV1) +uint32_t uart_compute_prescaler(UART_HandleTypeDef *huart) +{ + uint32_t prescaler = UART_PRESCALER_DIV1; + static const uint16_t presc_div[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; + uint32_t freq = uart_get_clock_source_freq(huart); + uint32_t usartdiv = 0; + +#if defined(UART_INSTANCE_LOWPOWER) + if (UART_INSTANCE_LOWPOWER(huart)) { + for (uint32_t idx = 0; idx < 12; idx++) { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(freq, huart->Init.BaudRate, presc_div[idx])); + if ((usartdiv >= 0x00000300U) && (usartdiv <= 0x000FFFFFU)) { + prescaler = UART_PRESCALER_DIV1 + idx; + break; + } + } + } else +#endif /* UART_INSTANCE_LOWPOWER */ + { + for (uint32_t idx = 0; idx < 12; idx++) { + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(freq, huart->Init.BaudRate, presc_div[idx])); + } else { + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(freq, huart->Init.BaudRate, presc_div[idx])); + } + if ((usartdiv >= 0x10U) && (usartdiv <= 0x0000FFFFU)) { + prescaler = UART_PRESCALER_DIV1 + idx; + break; + } + } + } + return prescaler; +} + +/** + * @brief Function called to get the clock source frequency of the uart + * @param huart : uart handle structure + * @retval uint32_t clock source frequency + */ +uint32_t uart_get_clock_source_freq(UART_HandleTypeDef *huart) +{ + uint32_t freq = 0; +#if defined(STM32WB0x) || defined(STM32WL3x) + freq = UART_PERIPHCLK; + if (UART_INSTANCE_LOWPOWER(huart)) { +#if defined(RCC_CFGR_LPUCLKSEL) + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPUART1); +#endif /* RCC_CFGR_LPUCLKSEL */ + } +#else /* STM32WB0x || STM32WL3x */ + uint32_t clocksource; + UART_GETCLOCKSOURCE(huart, clocksource); +#if defined(STM32H5) || defined(STM32MP1) || defined(STM32U0) ||\ + defined(STM32U3) || defined(STM32U5) + freq = HAL_RCCEx_GetPeriphCLKFreq(clocksource); +#else + switch (clocksource) { +#if defined(UART_CLOCKSOURCE_D2PCLK1) || defined(UART_CLOCKSOURCE_PCLK1) +#if defined(UART_CLOCKSOURCE_D2PCLK1) + case UART_CLOCKSOURCE_D2PCLK1: +#endif /* UART_CLOCKSOURCE_D2PCLK1*/ +#if defined(UART_CLOCKSOURCE_PCLK1) + case UART_CLOCKSOURCE_PCLK1: +#endif /* UART_CLOCKSOURCE_PCLK1 */ + freq = HAL_RCC_GetPCLK1Freq(); + break; +#endif /* UART_CLOCKSOURCE_D2PCLK1 || UART_CLOCKSOURCE_PCLK1*/ +#if defined(UART_CLOCKSOURCE_D2PCLK2) || defined(UART_CLOCKSOURCE_PCLK2) +#if defined(UART_CLOCKSOURCE_D2PCLK2) + case UART_CLOCKSOURCE_D2PCLK2: +#endif /* UART_CLOCKSOURCE_D2PCLK2*/ +#if defined(UART_CLOCKSOURCE_PCLK2) + case UART_CLOCKSOURCE_PCLK2: +#endif /* UART_CLOCKSOURCE_PCLK2 */ + freq = HAL_RCC_GetPCLK2Freq(); + break; +#endif /* UART_CLOCKSOURCE_D2PCLK2 || UART_CLOCKSOURCE_PCLK2*/ +#if defined(UART_CLOCKSOURCE_PCLK7) + case UART_CLOCKSOURCE_PCLK7: + freq = HAL_RCC_GetPCLK7Freq(); + break; +#endif /* UART_CLOCKSOURCE_PCLK7 */ +#if defined(UART_CLOCKSOURCE_PLL2) + case UART_CLOCKSOURCE_PLL2: + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + freq = pll2_clocks.PLL2_Q_Frequency; + break; + case UART_CLOCKSOURCE_PLL3: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + freq = pll3_clocks.PLL3_Q_Frequency; + break; +#endif /* UART_CLOCKSOURCE_PLL2 */ + case UART_CLOCKSOURCE_HSI: +#if defined(__HAL_RCC_GET_HSIKER_DIVIDER) + freq = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); +#else +#if defined(RCC_FLAG_HSIDIV) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { + freq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); + } else +#endif /* RCC_FLAG_HSIDIV */ + { + freq = (uint32_t) HSI_VALUE; + } +#endif + break; +#if defined(UART_CLOCKSOURCE_CSI) + case UART_CLOCKSOURCE_CSI: + freq = (uint32_t) CSI_VALUE; + break; +#endif /* UART_CLOCKSOURCE_CSI */ +#if defined(UART_CLOCKSOURCE_SYSCLK) + case UART_CLOCKSOURCE_SYSCLK: + freq = HAL_RCC_GetSysClockFreq(); + break; +#endif /* UART_CLOCKSOURCE_SYSCLK */ + case UART_CLOCKSOURCE_LSE: + freq = (uint32_t) LSE_VALUE; + break; + default: + freq = 0U; + break; + } +#endif /* STM32H5 */ +#endif /* STM32WB0x || STM32WL3x */ + return freq; +} +#endif /* UART_PRESCALER_DIV1 */ + #endif /* HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY */ #ifdef __cplusplus diff --git a/libraries/USBDevice/inc/USBSerial.h b/libraries/USBDevice/inc/USBSerial.h index 202c059daa..89b50cebcc 100644 --- a/libraries/USBDevice/inc/USBSerial.h +++ b/libraries/USBDevice/inc/USBSerial.h @@ -37,7 +37,15 @@ class USBSerial : public Stream { virtual int peek(void); virtual int read(void); virtual size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer + size_t readBytes(uint8_t *buffer, size_t length) + { + return readBytes((char *)buffer, length); + } virtual size_t readBytesUntil(char terminator, char *buffer, size_t length); // as readBytes with terminator character + size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) + { + return readBytesUntil(terminator, (char *)buffer, length); + } virtual void flush(void); virtual size_t write(uint8_t); virtual size_t write(const uint8_t *buffer, size_t size); diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index 001b3f4642..c097892803 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -193,9 +193,9 @@ static I2C_HandleTypeDef *i2c_handles[I2C_NUM]; static uint32_t i2c_getClkFreq(I2C_TypeDef *i2c) { uint32_t clkSrcFreq = 0; -#if defined(STM32WB0x) +#if defined(STM32WB0x) || defined(STM32WL3x) (void)i2c; // Avoid unused parameter warning - clkSrcFreq = SystemCoreClock; + clkSrcFreq = SystemCoreClock / 4; #else #ifdef STM32H7xx PLL3_ClocksTypeDef PLL3_Clocks; @@ -515,7 +515,7 @@ static uint32_t i2c_getClkFreq(I2C_TypeDef *i2c) } } #endif // I2C6_BASE -#endif /* STM32WB0x */ +#endif /* STM32WB0x || STM32WL3x */ return clkSrcFreq; } @@ -759,7 +759,8 @@ void i2c_init(i2c_t *obj, uint32_t timing, uint32_t ownAddress) obj->irq = I2C1_EV_IRQn; #if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ - !defined(STM32L0xx) && !defined(STM32U0xx) && !defined(STM32WB0x) + !defined(STM32L0xx) && !defined(STM32U0xx) && !defined(STM32WB0x) && \ + !defined(STM32WL3x) obj->irqER = I2C1_ER_IRQn; #endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ i2c_handles[I2C1_INDEX] = handle; @@ -773,7 +774,8 @@ void i2c_init(i2c_t *obj, uint32_t timing, uint32_t ownAddress) __HAL_RCC_I2C2_RELEASE_RESET(); obj->irq = I2C2_EV_IRQn; #if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ - !defined(STM32L0xx) && !defined(STM32U0xx) + !defined(STM32L0xx) && !defined(STM32U0xx) && !defined(STM32WB0x) && \ + !defined(STM32WL3x) obj->irqER = I2C2_ER_IRQn; #endif /* !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ i2c_handles[I2C2_INDEX] = handle; diff --git a/libraries/Wire/src/utility/twi.h b/libraries/Wire/src/utility/twi.h index 672ae02b38..22420ea4b7 100644 --- a/libraries/Wire/src/utility/twi.h +++ b/libraries/Wire/src/utility/twi.h @@ -69,7 +69,8 @@ extern "C" { /* Redefinition of IRQ for C0/F0/G0/L0/U0 families */ #if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) ||\ - defined(STM32L0xx) || defined(STM32U0xx) || defined(STM32WB0x) + defined(STM32L0xx) || defined(STM32U0xx) || defined(STM32WB0x) || \ + defined(STM32WL3x) #if defined(I2C1_BASE) #define I2C1_EV_IRQn I2C1_IRQn #define I2C1_EV_IRQHandler I2C1_IRQHandler diff --git a/platform.txt b/platform.txt index 58d8ca2d6f..1f29fda250 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.11.0 +version=2.12.0-dev # Define variables used multiple times in platform file @@ -120,6 +120,7 @@ upload.pid={upload.pid.0} upload.address=0x8000000 upload.mode=UR upload.start=0x8000000 +upload.parity=even # To customize the USB manufacturer or product string, must add defines # for them, e.g.: diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h index 0f7b82a572..23326fe545 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h @@ -214,7 +214,7 @@ typedef enum #define __FPU_PRESENT 1U /* FPU present */ #define __DSP_PRESENT 1U /* DSP extension present */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32l5xx.h" /*!< STM32L5xx System */ @@ -14729,7 +14729,7 @@ typedef struct /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32l5xx.h" /*!< STM32L5xx System */ @@ -15468,7 +15468,7 @@ typedef struct /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!Purpose

Update History

- +

Main Changes

Maintenance release

Contents

    -
  • Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
    • -
  • Add the READONLY tag to sections containing lookup tables to avoid GCC12 linker warnings if a segment is marked RWX.
    • +
  • Fix Capture Compare register TIMx_CCR5 definition.
    • +
  • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.
    • +
  • Update core_cm33 header file inclusion to use double quotes instead of angle brackets.

Notes

Reminder:

@@ -72,12 +73,41 @@

Notes

- +

Main Changes

Maintenance release

Contents

    +
  • Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
    • +
  • Add the READONLY tag to sections containing lookup tables to avoid GCC12 linker warnings if a segment is marked RWX.
    • +
+

Notes

+

Reminder:

+
    +
  • When TrustZone is enabled in the system (Flash option bit TZEN=1) +
      +
    • template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).
      • +
    • default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h: +
        +
      • SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)
        • +
      • SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))
        • +
      • SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))
        • +
      • SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)
        • +
      • SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)
        • +
      • SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+
  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
  • Add new atomic register access macros in stm32l5xx.h file.
    • @@ -85,7 +115,7 @@

    Contents

  • Add missing parameter after @param in order to fix warning in generated documentation
  • Change addresses of ROM symbols in sram.icf template files to code region alias in order to increase performance while running code from SRAM
-

Notes

+

Notes

Reminder:

  • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -107,9 +137,9 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    -

    Contents

    +

    Contents

    Maintenance release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

    • stm32l552xx.h and stm32l562xx.h updates @@ -118,7 +148,7 @@

      Contents

    • Fix I2C4_EV_IRQn and I2C4_ER_IRQn order in IRQn_Type
-

Notes

+

Notes

Reminder:

  • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -140,9 +170,9 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    Fourth release

    -

    Contents

    +

    Contents

    Fourth release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

    • stm32l552xx.h and stm32l562xx.h updates @@ -158,7 +188,7 @@

      Contents

    • Add README.md and License.md files for GitHub publication
    • Misspelled words corrections in driver descriptions
    -

    Notes

    +

    Notes

    Reminder:

    • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -180,9 +210,9 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      Third release

      -

      Contents

      +

      Contents

      Third official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

      • stm32l552xx.h and stm32l562xx.h updates @@ -192,7 +222,7 @@

        Contents

      • Align DBGMCU_APB2FZR register and bits definitions with RM0438
    -

    Notes

    +

    Notes

    Reminder:

    • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -214,9 +244,9 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      Second release

      -

      Contents

      +

      Contents

      Second official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

      • Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c @@ -224,7 +254,7 @@

        Contents

      • Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS
    -

    Notes

    +

    Notes

    Reminder:

    • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -246,9 +276,9 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      First release

      -

      Contents

      +

      Contents

      First official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

      • Templates @@ -266,7 +296,7 @@

        Contents

      • Linker files for 256 and 512 Kbytes Flash device configurations
    -

    Notes

    +

    Notes

    When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)

    diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c index 93e1ad7d1e..71f333cee3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c @@ -143,14 +143,14 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c index 53e22fff50..4b11eb8359 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c @@ -97,13 +97,19 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE_NS /*!< Vector Table base address field. This value must be a multiple of 0x200. */ +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x00018000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE_NS /*!< Vector Table base address field. This value must be a multiple of 0x200. */ +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x00040000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + #endif /* VECT_TAB_SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c index afe8e1ec68..b573073a11 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c @@ -159,14 +159,14 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE_S /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE_S /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h index 30773e1225..7131a7616f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/stm32u031xx.h @@ -578,7 +578,7 @@ typedef struct { __IO uint32_t CFGR1; /*!< SYSCFG Control register, Address offset: 0x00 */ uint32_t RESERVED0[5]; /*!< Reserved 0x04 --0x14 */ - uint32_t CFGR2; /*!< SYSCFG Class B register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG Class B register, Address offset: 0x18 */ __IO uint32_t SCSR; /*!< SYSCFG Backup Sram Erase Register, Address offset: 0x1C */ __IO uint32_t SKR; /*!< SYSCFG Backup Sram Key Register, Address offset: 0x20 */ __IO uint32_t TSCCR; /*!< SYSCFG TSC Comp Register, Address offset: 0x24 */ @@ -934,34 +934,34 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Pos (11UL) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ -#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Pos (13UL) #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ @@ -969,34 +969,34 @@ typedef struct #define ADC_ISR_EOSEQ (ADC_ISR_EOS) /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Pos (11UL) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ -#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Pos (13UL) #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ @@ -1004,87 +1004,87 @@ typedef struct #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Pos (0UL) #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Pos (1UL) #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Pos (2UL) #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ -#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Pos (3UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ -#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Pos (5UL) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ -#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Pos (6UL) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Pos (14UL) #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Pos (15UL) #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Pos (21UL) #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -1097,18 +1097,18 @@ typedef struct #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Pos (0UL) #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Pos (2UL) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -1116,101 +1116,101 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Pos (9UL) #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Pos (29UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ -#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Pos (30UL) #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_SMPR register ******************/ -#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Pos (0UL) #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ -#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Pos (4UL) #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Pos (8UL) #define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ -#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Pos (8UL) #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Pos (9UL) #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Pos (10UL) #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Pos (11UL) #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Pos (12UL) #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Pos (13UL) #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Pos (14UL) #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Pos (15UL) #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Pos (16UL) #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Pos (17UL) #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Pos (18UL) #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Pos (19UL) #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Pos (20UL) #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Pos (21UL) #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Pos (22UL) #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Pos (23UL) #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Pos (24UL) #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Pos (25UL) #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Pos (26UL) #define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ #define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR_SMPSEL19_Pos (27U) +#define ADC_SMPR_SMPSEL19_Pos (27UL) #define ADC_SMPR_SMPSEL19_Msk (0x1UL << ADC_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ #define ADC_SMPR_SMPSEL19 ADC_SMPR_SMPSEL19_Msk /*!< ADC channel 19 sampling time selection */ /******************** Bit definition for ADC_AWD1TR register *******************/ -#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Pos (0UL) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ @@ -1226,7 +1226,7 @@ typedef struct #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ -#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Pos (16UL) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ @@ -1243,7 +1243,7 @@ typedef struct #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWD2TR register *******************/ -#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Pos (0UL) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ @@ -1259,7 +1259,7 @@ typedef struct #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ -#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Pos (16UL) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ @@ -1276,84 +1276,84 @@ typedef struct #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_CHSELR register ****************/ -#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Pos (0UL) #define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Pos (22UL) #define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Pos (21UL) #define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ #define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Pos (20UL) #define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ #define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Pos (19UL) #define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ #define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Pos (18UL) #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Pos (17UL) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Pos (16UL) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Pos (15UL) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Pos (14UL) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Pos (13UL) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Pos (12UL) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Pos (11UL) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Pos (10UL) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Pos (9UL) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Pos (8UL) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Pos (7UL) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Pos (6UL) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Pos (5UL) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Pos (4UL) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Pos (3UL) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Pos (2UL) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Pos (1UL) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Pos (0UL) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Pos (0UL) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Pos (28UL) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ @@ -1361,7 +1361,7 @@ typedef struct #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ -#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Pos (24UL) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ @@ -1369,7 +1369,7 @@ typedef struct #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ -#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Pos (20UL) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ @@ -1377,7 +1377,7 @@ typedef struct #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ -#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Pos (16UL) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ @@ -1385,7 +1385,7 @@ typedef struct #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ -#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Pos (12UL) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ @@ -1393,7 +1393,7 @@ typedef struct #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Pos (8UL) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ @@ -1401,7 +1401,7 @@ typedef struct #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Pos (4UL) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ @@ -1409,7 +1409,7 @@ typedef struct #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Pos (0UL) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ @@ -1418,7 +1418,7 @@ typedef struct #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ /******************** Bit definition for ADC_AWD3TR register *******************/ -#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Pos (0UL) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ @@ -1434,7 +1434,7 @@ typedef struct #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ -#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Pos (16UL) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ @@ -1451,7 +1451,7 @@ typedef struct #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Pos (0UL) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ @@ -1472,7 +1472,7 @@ typedef struct #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -1496,7 +1496,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -1520,7 +1520,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Pos (0UL) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -1533,7 +1533,7 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -1541,13 +1541,13 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23UL) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to VBATEN sensor enable */ @@ -1558,49 +1558,49 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ #define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */ -#define CRC_CR_RTYPE_IN_Pos (9U) +#define CRC_CR_RTYPE_IN_Pos (9UL) #define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */ #define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */ -#define CRC_CR_RTYPE_OUT_Pos (10U) +#define CRC_CR_RTYPE_OUT_Pos (10UL) #define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */ #define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ @@ -1609,14 +1609,14 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6221,85 +6216,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6308,86 +6303,86 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -6397,279 +6392,279 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Pos (19UL) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1POM_Pos (0U) +#define TAMP_CR2_TAMP1POM_Pos (0UL) #define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk -#define TAMP_CR2_TAMP2POM_Pos (1U) +#define TAMP_CR2_TAMP2POM_Pos (1UL) #define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk -#define TAMP_CR2_TAMP3POM_Pos (2U) +#define TAMP_CR2_TAMP3POM_Pos (2UL) #define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk -#define TAMP_CR2_TAMP4POM_Pos (3U) +#define TAMP_CR2_TAMP4POM_Pos (3UL) #define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk -#define TAMP_CR2_TAMP5POM_Pos (4U) +#define TAMP_CR2_TAMP5POM_Pos (4UL) #define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP3POM_Pos (2U) +#define TAMP_CR3_ITAMP3POM_Pos (2UL) #define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk -#define TAMP_CR3_ITAMP4POM_Pos (3U) +#define TAMP_CR3_ITAMP4POM_Pos (3UL) #define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk -#define TAMP_CR3_ITAMP5POM_Pos (4U) +#define TAMP_CR3_ITAMP5POM_Pos (4UL) #define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6POM_Pos (5U) -#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk +#define TAMP_CR3_ITAMP6POM_Pos (5UL) +#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Pos (19UL) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Pos (19UL) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk /******************** Bits definition for TAMP_MISR register ************ *****/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Pos (19UL) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Pos (19UL) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Number of backup registers ******************************/ -#define TAMP_BKP_NUMBER_Pos (4U) +#define TAMP_BKP_NUMBER_Pos (4UL) #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */ #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 9 BKPREG */ @@ -6683,152 +6678,152 @@ typedef struct */ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0UL) #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[17] */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0UL) #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1UL) #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2UL) #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3UL) #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0UL) #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE14_SR_TIM1_CC1 SYSCFG_ITLINE14_SR_TIM1_CC1_Msk /*!< TIM1 CC1 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1U) +#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1UL) #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE14_SR_TIM1_CC2 SYSCFG_ITLINE14_SR_TIM1_CC2_Msk /*!< TIM1 CC2 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2U) +#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2UL) #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE14_SR_TIM1_CC3 SYSCFG_ITLINE14_SR_TIM1_CC3_Msk /*!< TIM1 CC3 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3U) +#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3UL) #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE14_SR_TIM1_CC4 SYSCFG_ITLINE14_SR_TIM1_CC4_Msk /*!< TIM1 CC4 Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_Pos (0UL) #define SYSCFG_ITLINE15_SR_TIM2_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE15_SR_TIM2 SYSCFG_ITLINE15_SR_TIM2_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_Pos (0UL) #define SYSCFG_ITLINE16_SR_TIM3_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE16_SR_TIM3 SYSCFG_ITLINE16_SR_TIM3_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_Pos (0UL) #define SYSCFG_ITLINE17_SR_TIM6_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE17_SR_TIM6 SYSCFG_ITLINE17_SR_TIM6_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Pos (1UL) #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2UL) #define SYSCFG_ITLINE17_SR_LPTIM1_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE17_SR_LPTIM1 SYSCFG_ITLINE17_SR_LPTIM1_Msk /*!< LPTIM1 -> exti[24] Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_Pos (0UL) #define SYSCFG_ITLINE18_SR_TIM7_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE18_SR_TIM7 SYSCFG_ITLINE18_SR_TIM7_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1UL) #define SYSCFG_ITLINE18_SR_LPTIM2_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE18_SR_LPTIM2 SYSCFG_ITLINE18_SR_LPTIM2_Msk /*!< LPTIM2 -> exti[25] Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM15_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM15_Pos (0UL) #define SYSCFG_ITLINE19_SR_TIM15_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE19_SR_TIM15 SYSCFG_ITLINE19_SR_TIM15_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE20_SR_TIM16_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM16_Pos (0UL) #define SYSCFG_ITLINE20_SR_TIM16_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE20_SR_TIM16 SYSCFG_ITLINE20_SR_TIM16_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0U) +#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0UL) #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_MCE SYSCFG_ITLINE21_SR_TSC_MCE_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1U) +#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1UL) #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_EOA SYSCFG_ITLINE21_SR_TSC_EOA_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_Pos (0UL) #define SYSCFG_ITLINE23_SR_I2C1_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE23_SR_I2C1 SYSCFG_ITLINE23_SR_I2C1_Msk /*!< I2C1 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C2_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_Pos (0UL) #define SYSCFG_ITLINE24_SR_I2C2_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE24_SR_I2C2 SYSCFG_ITLINE24_SR_I2C2_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C4_Pos (1U) +#define SYSCFG_ITLINE24_SR_I2C4_Pos (1UL) #define SYSCFG_ITLINE24_SR_I2C4_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE24_SR_I2C4 SYSCFG_ITLINE24_SR_I2C4_Msk /*!< I2C3 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C3_Pos (2U) +#define SYSCFG_ITLINE24_SR_I2C3_Pos (2UL) #define SYSCFG_ITLINE24_SR_I2C3_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE24_SR_I2C3 SYSCFG_ITLINE24_SR_I2C3_Msk /*!< I2C3 GLB Interrupt -> exti[23]*/ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0UL) #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0UL) #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_Pos (0UL) #define SYSCFG_ITLINE27_SR_USART1_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE27_SR_USART1 SYSCFG_ITLINE27_SR_USART1_Msk /*!< USART1 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_USART2_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_Pos (0UL) #define SYSCFG_ITLINE28_SR_USART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE28_SR_USART2 SYSCFG_ITLINE28_SR_USART2_Msk /*!< USART2 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1U) +#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1UL) #define SYSCFG_ITLINE28_SR_LPUART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE28_SR_LPUART2 SYSCFG_ITLINE28_SR_LPUART2_Msk /*!< LPUART2 GLB Interrupt -> exti[31] */ -#define SYSCFG_ITLINE29_SR_USART3_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_Pos (0UL) #define SYSCFG_ITLINE29_SR_USART3_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE29_SR_USART3 SYSCFG_ITLINE29_SR_USART3_Msk /*!< USART3 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1U) +#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1UL) #define SYSCFG_ITLINE29_SR_LPUART1_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE29_SR_LPUART1 SYSCFG_ITLINE29_SR_LPUART1_Msk /*!< LPUART1 GLB Interrupt -> exti[30] */ -#define SYSCFG_ITLINE30_SR_USART4_Pos (0U) +#define SYSCFG_ITLINE30_SR_USART4_Pos (0UL) #define SYSCFG_ITLINE30_SR_USART4_Msk (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE30_SR_USART4 SYSCFG_ITLINE30_SR_USART4_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Pos (0UL) #define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ @@ -7178,92 +7173,92 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0UL) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6849,85 +6844,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -6936,86 +6931,86 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -7025,279 +7020,279 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Pos (19UL) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1POM_Pos (0U) +#define TAMP_CR2_TAMP1POM_Pos (0UL) #define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk -#define TAMP_CR2_TAMP2POM_Pos (1U) +#define TAMP_CR2_TAMP2POM_Pos (1UL) #define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk -#define TAMP_CR2_TAMP3POM_Pos (2U) +#define TAMP_CR2_TAMP3POM_Pos (2UL) #define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk -#define TAMP_CR2_TAMP4POM_Pos (3U) +#define TAMP_CR2_TAMP4POM_Pos (3UL) #define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk -#define TAMP_CR2_TAMP5POM_Pos (4U) +#define TAMP_CR2_TAMP5POM_Pos (4UL) #define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP3POM_Pos (2U) +#define TAMP_CR3_ITAMP3POM_Pos (2UL) #define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk -#define TAMP_CR3_ITAMP4POM_Pos (3U) +#define TAMP_CR3_ITAMP4POM_Pos (3UL) #define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk -#define TAMP_CR3_ITAMP5POM_Pos (4U) +#define TAMP_CR3_ITAMP5POM_Pos (4UL) #define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6POM_Pos (5U) -#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk +#define TAMP_CR3_ITAMP6POM_Pos (5UL) +#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Pos (19UL) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Pos (19UL) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk /******************** Bits definition for TAMP_MISR register ************ *****/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Pos (19UL) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Pos (19UL) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Number of backup registers ******************************/ -#define TAMP_BKP_NUMBER_Pos (4U) +#define TAMP_BKP_NUMBER_Pos (4UL) #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */ #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 9 BKPREG */ @@ -7311,152 +7306,152 @@ typedef struct */ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0UL) #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[17] */ -#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2UL) #define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0UL) #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1UL) #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2UL) #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3UL) #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0UL) #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE14_SR_TIM1_CC1 SYSCFG_ITLINE14_SR_TIM1_CC1_Msk /*!< TIM1 CC1 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1U) +#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1UL) #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE14_SR_TIM1_CC2 SYSCFG_ITLINE14_SR_TIM1_CC2_Msk /*!< TIM1 CC2 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2U) +#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2UL) #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE14_SR_TIM1_CC3 SYSCFG_ITLINE14_SR_TIM1_CC3_Msk /*!< TIM1 CC3 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3U) +#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3UL) #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE14_SR_TIM1_CC4 SYSCFG_ITLINE14_SR_TIM1_CC4_Msk /*!< TIM1 CC4 Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_Pos (0UL) #define SYSCFG_ITLINE15_SR_TIM2_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE15_SR_TIM2 SYSCFG_ITLINE15_SR_TIM2_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_Pos (0UL) #define SYSCFG_ITLINE16_SR_TIM3_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE16_SR_TIM3 SYSCFG_ITLINE16_SR_TIM3_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_Pos (0UL) #define SYSCFG_ITLINE17_SR_TIM6_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE17_SR_TIM6 SYSCFG_ITLINE17_SR_TIM6_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Pos (1UL) #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2UL) #define SYSCFG_ITLINE17_SR_LPTIM1_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE17_SR_LPTIM1 SYSCFG_ITLINE17_SR_LPTIM1_Msk /*!< LPTIM1 -> exti[24] Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_Pos (0UL) #define SYSCFG_ITLINE18_SR_TIM7_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE18_SR_TIM7 SYSCFG_ITLINE18_SR_TIM7_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1UL) #define SYSCFG_ITLINE18_SR_LPTIM2_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE18_SR_LPTIM2 SYSCFG_ITLINE18_SR_LPTIM2_Msk /*!< LPTIM2 -> exti[25] Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM15_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM15_Pos (0UL) #define SYSCFG_ITLINE19_SR_TIM15_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE19_SR_TIM15 SYSCFG_ITLINE19_SR_TIM15_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1U) +#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1UL) #define SYSCFG_ITLINE19_SR_LPTIM3_Msk (0x1UL << SYSCFG_ITLINE19_SR_LPTIM3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE19_SR_LPTIM3 SYSCFG_ITLINE19_SR_LPTIM3_Msk /*!< LPTIM3 GLB Interrupt -> exti [26]*/ -#define SYSCFG_ITLINE20_SR_TIM16_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM16_Pos (0UL) #define SYSCFG_ITLINE20_SR_TIM16_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE20_SR_TIM16 SYSCFG_ITLINE20_SR_TIM16_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0U) +#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0UL) #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_MCE SYSCFG_ITLINE21_SR_TSC_MCE_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1U) +#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1UL) #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_EOA SYSCFG_ITLINE21_SR_TSC_EOA_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE22_SR_LCD_Pos (0U) +#define SYSCFG_ITLINE22_SR_LCD_Pos (0UL) #define SYSCFG_ITLINE22_SR_LCD_Msk (0x1UL << SYSCFG_ITLINE22_SR_LCD_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE22_SR_LCD SYSCFG_ITLINE22_SR_LCD_Msk /*!< LCD GLB Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_Pos (0UL) #define SYSCFG_ITLINE23_SR_I2C1_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE23_SR_I2C1 SYSCFG_ITLINE23_SR_I2C1_Msk /*!< I2C1 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C2_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_Pos (0UL) #define SYSCFG_ITLINE24_SR_I2C2_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE24_SR_I2C2 SYSCFG_ITLINE24_SR_I2C2_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C4_Pos (1U) +#define SYSCFG_ITLINE24_SR_I2C4_Pos (1UL) #define SYSCFG_ITLINE24_SR_I2C4_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE24_SR_I2C4 SYSCFG_ITLINE24_SR_I2C4_Msk /*!< I2C3 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C3_Pos (2U) +#define SYSCFG_ITLINE24_SR_I2C3_Pos (2UL) #define SYSCFG_ITLINE24_SR_I2C3_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE24_SR_I2C3 SYSCFG_ITLINE24_SR_I2C3_Msk /*!< I2C3 GLB Interrupt -> exti[23]*/ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0UL) #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0UL) #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI3_Pos (1U) +#define SYSCFG_ITLINE26_SR_SPI3_Pos (1UL) #define SYSCFG_ITLINE26_SR_SPI3_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE26_SR_SPI3 SYSCFG_ITLINE26_SR_SPI3_Msk /*!< SPI3 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_Pos (0UL) #define SYSCFG_ITLINE27_SR_USART1_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE27_SR_USART1 SYSCFG_ITLINE27_SR_USART1_Msk /*!< USART1 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_USART2_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_Pos (0UL) #define SYSCFG_ITLINE28_SR_USART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE28_SR_USART2 SYSCFG_ITLINE28_SR_USART2_Msk /*!< USART2 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1U) +#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1UL) #define SYSCFG_ITLINE28_SR_LPUART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE28_SR_LPUART2 SYSCFG_ITLINE28_SR_LPUART2_Msk /*!< LPUART2 GLB Interrupt -> exti[31] */ -#define SYSCFG_ITLINE29_SR_USART3_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_Pos (0UL) #define SYSCFG_ITLINE29_SR_USART3_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE29_SR_USART3 SYSCFG_ITLINE29_SR_USART3_Msk /*!< USART3 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1U) +#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1UL) #define SYSCFG_ITLINE29_SR_LPUART1_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE29_SR_LPUART1 SYSCFG_ITLINE29_SR_LPUART1_Msk /*!< LPUART1 GLB Interrupt -> exti[30] */ -#define SYSCFG_ITLINE30_SR_USART4_Pos (0U) +#define SYSCFG_ITLINE30_SR_USART4_Pos (0UL) #define SYSCFG_ITLINE30_SR_USART4_Msk (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE30_SR_USART4 SYSCFG_ITLINE30_SR_USART4_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1U) +#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1UL) #define SYSCFG_ITLINE30_SR_LPUART3_Msk (0x1UL << SYSCFG_ITLINE30_SR_LPUART3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE30_SR_LPUART3 SYSCFG_ITLINE30_SR_LPUART3_Msk /*!< LPUART3 GLB Interrupt */ -#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Pos (0UL) #define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ @@ -7845,92 +7840,92 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0UL) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -7116,85 +7111,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -7203,86 +7198,86 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -7292,279 +7287,279 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Pos (19UL) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1POM_Pos (0U) +#define TAMP_CR2_TAMP1POM_Pos (0UL) #define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk -#define TAMP_CR2_TAMP2POM_Pos (1U) +#define TAMP_CR2_TAMP2POM_Pos (1UL) #define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk -#define TAMP_CR2_TAMP3POM_Pos (2U) +#define TAMP_CR2_TAMP3POM_Pos (2UL) #define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk -#define TAMP_CR2_TAMP4POM_Pos (3U) +#define TAMP_CR2_TAMP4POM_Pos (3UL) #define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk -#define TAMP_CR2_TAMP5POM_Pos (4U) +#define TAMP_CR2_TAMP5POM_Pos (4UL) #define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x04000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP3POM_Pos (2U) +#define TAMP_CR3_ITAMP3POM_Pos (2UL) #define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk -#define TAMP_CR3_ITAMP4POM_Pos (3U) +#define TAMP_CR3_ITAMP4POM_Pos (3UL) #define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk -#define TAMP_CR3_ITAMP5POM_Pos (4U) +#define TAMP_CR3_ITAMP5POM_Pos (4UL) #define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6POM_Pos (5U) -#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6tPOM_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk +#define TAMP_CR3_ITAMP6POM_Pos (5UL) +#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Pos (19UL) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Pos (19UL) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk /******************** Bits definition for TAMP_MISR register ************ *****/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Pos (19UL) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Pos (19UL) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Number of backup registers ******************************/ -#define TAMP_BKP_NUMBER_Pos (4U) +#define TAMP_BKP_NUMBER_Pos (4UL) #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */ #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 9 BKPREG */ @@ -7578,152 +7573,152 @@ typedef struct */ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Pos (0UL) #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[17] */ -#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2UL) #define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ -#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0UL) #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1UL) #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2UL) #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ -#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3UL) #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC1_Pos (0UL) #define SYSCFG_ITLINE14_SR_TIM1_CC1_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE14_SR_TIM1_CC1 SYSCFG_ITLINE14_SR_TIM1_CC1_Msk /*!< TIM1 CC1 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1U) +#define SYSCFG_ITLINE14_SR_TIM1_CC2_Pos (1UL) #define SYSCFG_ITLINE14_SR_TIM1_CC2_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE14_SR_TIM1_CC2 SYSCFG_ITLINE14_SR_TIM1_CC2_Msk /*!< TIM1 CC2 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2U) +#define SYSCFG_ITLINE14_SR_TIM1_CC3_Pos (2UL) #define SYSCFG_ITLINE14_SR_TIM1_CC3_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE14_SR_TIM1_CC3 SYSCFG_ITLINE14_SR_TIM1_CC3_Msk /*!< TIM1 CC3 Interrupt */ -#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3U) +#define SYSCFG_ITLINE14_SR_TIM1_CC4_Pos (3UL) #define SYSCFG_ITLINE14_SR_TIM1_CC4_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC4_Pos) /*!< 0x00000008 */ #define SYSCFG_ITLINE14_SR_TIM1_CC4 SYSCFG_ITLINE14_SR_TIM1_CC4_Msk /*!< TIM1 CC4 Interrupt */ -#define SYSCFG_ITLINE15_SR_TIM2_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_Pos (0UL) #define SYSCFG_ITLINE15_SR_TIM2_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE15_SR_TIM2 SYSCFG_ITLINE15_SR_TIM2_Msk /*!< TIM2 GLB Interrupt */ -#define SYSCFG_ITLINE16_SR_TIM3_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_Pos (0UL) #define SYSCFG_ITLINE16_SR_TIM3_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE16_SR_TIM3 SYSCFG_ITLINE16_SR_TIM3_Msk /*!< TIM3 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_TIM6_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_Pos (0UL) #define SYSCFG_ITLINE17_SR_TIM6_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE17_SR_TIM6 SYSCFG_ITLINE17_SR_TIM6_Msk /*!< TIM6 GLB Interrupt */ -#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Pos (1UL) #define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ -#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_Pos (2UL) #define SYSCFG_ITLINE17_SR_LPTIM1_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE17_SR_LPTIM1 SYSCFG_ITLINE17_SR_LPTIM1_Msk /*!< LPTIM1 -> exti[24] Interrupt */ -#define SYSCFG_ITLINE18_SR_TIM7_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_Pos (0UL) #define SYSCFG_ITLINE18_SR_TIM7_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE18_SR_TIM7 SYSCFG_ITLINE18_SR_TIM7_Msk /*!< TIM7 GLB Interrupt */ -#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_Pos (1UL) #define SYSCFG_ITLINE18_SR_LPTIM2_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE18_SR_LPTIM2 SYSCFG_ITLINE18_SR_LPTIM2_Msk /*!< LPTIM2 -> exti[25] Interrupt */ -#define SYSCFG_ITLINE19_SR_TIM15_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM15_Pos (0UL) #define SYSCFG_ITLINE19_SR_TIM15_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM15_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE19_SR_TIM15 SYSCFG_ITLINE19_SR_TIM15_Msk /*!< TIM15 GLB Interrupt */ -#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1U) +#define SYSCFG_ITLINE19_SR_LPTIM3_Pos (1UL) #define SYSCFG_ITLINE19_SR_LPTIM3_Msk (0x1UL << SYSCFG_ITLINE19_SR_LPTIM3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE19_SR_LPTIM3 SYSCFG_ITLINE19_SR_LPTIM3_Msk /*!< LPTIM3 GLB Interrupt -> exti [26]*/ -#define SYSCFG_ITLINE20_SR_TIM16_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM16_Pos (0UL) #define SYSCFG_ITLINE20_SR_TIM16_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM16_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE20_SR_TIM16 SYSCFG_ITLINE20_SR_TIM16_Msk /*!< TIM16 GLB Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0U) +#define SYSCFG_ITLINE21_SR_TSC_MCE_Pos (0UL) #define SYSCFG_ITLINE21_SR_TSC_MCE_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_MCE_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_MCE SYSCFG_ITLINE21_SR_TSC_MCE_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1U) +#define SYSCFG_ITLINE21_SR_TSC_EOA_Pos (1UL) #define SYSCFG_ITLINE21_SR_TSC_EOA_Msk (0x1UL << SYSCFG_ITLINE21_SR_TSC_EOA_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE21_SR_TSC_EOA SYSCFG_ITLINE21_SR_TSC_EOA_Msk /*!< TSC_MCE Interrupt */ -#define SYSCFG_ITLINE22_SR_LCD_Pos (0U) +#define SYSCFG_ITLINE22_SR_LCD_Pos (0UL) #define SYSCFG_ITLINE22_SR_LCD_Msk (0x1UL << SYSCFG_ITLINE22_SR_LCD_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE22_SR_LCD SYSCFG_ITLINE22_SR_LCD_Msk /*!< LCD GLB Interrupt */ -#define SYSCFG_ITLINE23_SR_I2C1_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_Pos (0UL) #define SYSCFG_ITLINE23_SR_I2C1_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE23_SR_I2C1 SYSCFG_ITLINE23_SR_I2C1_Msk /*!< I2C1 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C2_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_Pos (0UL) #define SYSCFG_ITLINE24_SR_I2C2_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE24_SR_I2C2 SYSCFG_ITLINE24_SR_I2C2_Msk /*!< I2C2 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C4_Pos (1U) +#define SYSCFG_ITLINE24_SR_I2C4_Pos (1UL) #define SYSCFG_ITLINE24_SR_I2C4_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE24_SR_I2C4 SYSCFG_ITLINE24_SR_I2C4_Msk /*!< I2C3 GLB Interrupt */ -#define SYSCFG_ITLINE24_SR_I2C3_Pos (2U) +#define SYSCFG_ITLINE24_SR_I2C3_Pos (2UL) #define SYSCFG_ITLINE24_SR_I2C3_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C3_Pos) /*!< 0x00000004 */ #define SYSCFG_ITLINE24_SR_I2C3 SYSCFG_ITLINE24_SR_I2C3_Msk /*!< I2C3 GLB Interrupt -> exti[23]*/ -#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0UL) #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0UL) #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ -#define SYSCFG_ITLINE26_SR_SPI3_Pos (1U) +#define SYSCFG_ITLINE26_SR_SPI3_Pos (1UL) #define SYSCFG_ITLINE26_SR_SPI3_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE26_SR_SPI3 SYSCFG_ITLINE26_SR_SPI3_Msk /*!< SPI3 Interrupt */ -#define SYSCFG_ITLINE27_SR_USART1_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_Pos (0UL) #define SYSCFG_ITLINE27_SR_USART1_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE27_SR_USART1 SYSCFG_ITLINE27_SR_USART1_Msk /*!< USART1 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_USART2_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_Pos (0UL) #define SYSCFG_ITLINE28_SR_USART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE28_SR_USART2 SYSCFG_ITLINE28_SR_USART2_Msk /*!< USART2 GLB Interrupt */ -#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1U) +#define SYSCFG_ITLINE28_SR_LPUART2_Pos (1UL) #define SYSCFG_ITLINE28_SR_LPUART2_Msk (0x1UL << SYSCFG_ITLINE28_SR_LPUART2_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE28_SR_LPUART2 SYSCFG_ITLINE28_SR_LPUART2_Msk /*!< LPUART2 GLB Interrupt -> exti[31] */ -#define SYSCFG_ITLINE29_SR_USART3_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_Pos (0UL) #define SYSCFG_ITLINE29_SR_USART3_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE29_SR_USART3 SYSCFG_ITLINE29_SR_USART3_Msk /*!< USART3 GLB Interrupt */ -#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1U) +#define SYSCFG_ITLINE29_SR_LPUART1_Pos (1UL) #define SYSCFG_ITLINE29_SR_LPUART1_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE29_SR_LPUART1 SYSCFG_ITLINE29_SR_LPUART1_Msk /*!< LPUART1 GLB Interrupt -> exti[30] */ -#define SYSCFG_ITLINE30_SR_USART4_Pos (0U) +#define SYSCFG_ITLINE30_SR_USART4_Pos (0UL) #define SYSCFG_ITLINE30_SR_USART4_Msk (0x1UL << SYSCFG_ITLINE30_SR_USART4_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE30_SR_USART4 SYSCFG_ITLINE30_SR_USART4_Msk /*!< USART4 GLB Interrupt */ -#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1U) +#define SYSCFG_ITLINE30_SR_LPUART3_Pos (1UL) #define SYSCFG_ITLINE30_SR_LPUART3_Msk (0x1UL << SYSCFG_ITLINE30_SR_LPUART3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE30_SR_LPUART3 SYSCFG_ITLINE30_SR_LPUART3_Msk /*!< LPUART3 GLB Interrupt */ -#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Pos (0UL) #define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ -#define SYSCFG_ITLINE31_SR_AES_Pos (1U) +#define SYSCFG_ITLINE31_SR_AES_Pos (1UL) #define SYSCFG_ITLINE31_SR_AES_Msk (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE31_SR_AES SYSCFG_ITLINE31_SR_AES_Msk /*!< AES Interrupt */ @@ -8115,92 +8110,92 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Pos (0UL) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!Release Notes for  STM32U0xx C

    Update History

    - +

    Main Changes

    • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
        +
      • Added specific linker files for STM32U073xB and STM32U073x8 devices.
        • +
      • Updated system_stm32u0xx.c file to allow ‘VECT_TAB_OFFSET’ to be overridden externally (by IDE or Makefile).
        • +
      • BOR bits configuration and definition aligned with the STM32U0 reference manual.
        • +
      • Rename AES suspend registers according last update in STM32U0 reference manual.
        • +
      • +
    +

    +
    +
    +
    + +
    +

    Main Changes

    +
      +
    • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual). +
      • Fixed the right CFGR_HPRE shift in the SystemCoreClockUpdate API.
      • Align the ErrorStatus typedef declaration with HAL_StatusTypeDef.
      • Add the address to use for the bootloader jump service.
    -

    +

    -

    Main Changes

    +

    Main Changes

    • CMSIS Device Maintenance Release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
        @@ -55,17 +71,17 @@

        Main Changes

      • Removed the I2C_CR1_SWRST bit definition.
    -

    +

    -

    Main Changes

    +

    Main Changes

    • First official release version of bits and registers definition aligned with the RM0503 (STM32U0 reference manual).
    -

    +

    diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld new file mode 100644 index 0000000000..80be06cdac --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073x8_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U073x8 Device from STM32U0 series +** 64Kbytes FLASH +** 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld new file mode 100644 index 0000000000..9877f8de03 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/linker/STM32U073xB_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32U073xB Device from STM32U0 series +** 128Kbytes FLASH +** 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c index ab4b081111..340c680b84 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c @@ -117,8 +117,10 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ //#define VECT_TAB_SRAM +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ /*!< Comment the following line if you would like to disable the software workaround related to debug access in case RDP=1 and Boot_Lock=1 */ @@ -327,7 +329,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; + tmp = AHBPrescTable[(((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h new file mode 100644 index 0000000000..279b943469 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3x.h @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file stm32wl3x.h + * @author MCD Application Team + * @brief CMSIS STM32WL3x Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32WBxx device used in the target application + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32wl3x + * @{ + */ + +#ifndef STM32WL3x_H +#define STM32WL3x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32WL3) +#define STM32WL3 +#endif /* STM32WL3 */ + +/** Uncomment the line below according to the target STM32WL3 device used in your application. + * stm32wl3xx.h file contains: + * - All the peripheral register's definitions, bits definitions and memory mapping for STM32WL3xx devices + * - IRQ channel definition + * - Peripheral memory mapping and physical registers address definition + * - Peripheral pointer declaration and driver header file inclusion + * - Product miscellaneous configuration: assert macros, … + * Note: These CMSIS drivers (stm32wl3xx.h) are always supporting features of the sub-family's superset. + */ +#if !defined (STM32WL3XX) + /* #define STM32WL3XX */ /*!< STM32WL30x, STM32WL31x and STM32WL33x Devices */ +#endif /* STM32WL3XX */ + +/* Legacy aliases */ +#if defined (STM32WL33) + #define STM32WL3XX +#endif /* STM32WL33 */ + + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32WL3x_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32WL3x_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WL3x_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WL3x_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WL3x_CMSIS_VERSION ((__STM32WL3x_CMSIS_VERSION_MAIN << 24U)\ + |(__STM32WL3x_CMSIS_VERSION_SUB1 << 16U)\ + |(__STM32WL3x_CMSIS_VERSION_SUB2 << 8U )\ + |(__STM32WL3x_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +/* Fix issue with case sensitive definition in stm32wl3x.h */ +#if defined(STM32WL3xx) + #define STM32WL3XX +#endif +#if defined(STM32WL3XX) + #include "stm32wl3xx.h" +#else + #error "Please select first the target STM32WL3xx device used in your application (in stm32wl3x.h file)" +#endif /* STM32WL3XX */ + +/** + * @} + */ + +/** @addtogroup Exported types + * @{ + */ + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +typedef uint8_t BOOL; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ + +/**@brief Macro that checks if STATE is a FlagStatus / ITStatus */ +#define IS_FLAGSTATUS(STATE) (((STATE) == RESET) || ((STATE) == SET)) +#define IS_ITSTATUS(STATE) IS_FLAGSTATUS(STATE) + +/** @brief Macro that checks if STATE is a FunctionalState */ +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +/** @brief Macro that returns a 16-bit value from a buffer where the value is stored in Little Endian Format */ +#define LE_TO_HOST_16(ptr) (uint16_t) ( ((uint16_t)*((uint8_t *)(ptr))) | \ + ((uint16_t)*((uint8_t *)(ptr) + 1) << 8) ) + +/** @brief Macro that returns a 16-bit value from a buffer where the value is stored in Big Endian Format */ +#define BE_TO_HOST_16(ptr) (uint16_t) ( ((uint16_t) *((uint8_t *)ptr)) << 8 | \ + ((uint16_t) *((uint8_t *)ptr + 1) ) ) + +/** @brief Macro that stores a 16-bit value into a buffer in Little Endian Format (2 bytes) */ +#define HOST_TO_LE_16(buf, val) ( ((buf)[0] = (uint8_t) (val) ) , \ + ((buf)[1] = (uint8_t) ((val)>>8) ) ) + +/** @brief Macro that returns a 32-bit value from a buffer where the value is stored in Little Endian Format */ +#define LE_TO_HOST_32(ptr) (uint32_t) ( ((uint32_t)*((uint8_t *)(ptr))) | \ + ((uint32_t)*((uint8_t *)(ptr) + 1) << 8) | \ + ((uint32_t)*((uint8_t *)(ptr) + 2) << 16) | \ + ((uint32_t)*((uint8_t *)(ptr) + 3) << 24) ) + +/** @brief Macro that returns a 16-bit value from a buffer where the value is stored in Big Endian Format */ +#define BE_TO_HOST_32(ptr) (uint32_t) ( ((uint32_t) *((uint8_t *)ptr )) << 24 | \ + ((uint32_t) *((uint8_t *)ptr + 1)) << 16 | \ + ((uint32_t) *((uint8_t *)ptr + 2)) << 8 | \ + ((uint32_t) *((uint8_t *)ptr + 3)) ) + +/** @brief Macro that stores a 32-bit value into a buffer in Little Endian Format (4 bytes) */ +#define HOST_TO_LE_32(buf, val) ( ((buf)[0] = (uint8_t) (val) ) , \ + ((buf)[1] = (uint8_t) ((val)>>8) ) , \ + ((buf)[2] = (uint8_t) ((val)>>16) ) , \ + ((buf)[3] = (uint8_t) ((val)>>24) ) ) + +/** @brief Macro that returns a 64-bit value from a buffer where the value is stored in Little Endian Format */ +#define LE_TO_HOST_64(ptr) (uint64_t) ( ((uint64_t)*((uint8_t *)(ptr))) | \ + ((uint64_t)*((uint8_t *)(ptr) + 1) << 8) | \ + ((uint64_t)*((uint8_t *)(ptr) + 2) << 16) | \ + ((uint64_t)*((uint8_t *)(ptr) + 3) << 24) | \ + ((uint64_t)*((uint8_t *)(ptr) + 4) << 32) | \ + ((uint64_t)*((uint8_t *)(ptr) + 5) << 40) | \ + ((uint64_t)*((uint8_t *)(ptr) + 6) << 48) | \ + ((uint64_t)*((uint8_t *)(ptr) + 7) << 56) ) + +/** @brief Macro that stores a 64-bit value into a buffer in Little Endian Format (8 bytes) */ +#define HOST_TO_LE_64(buf, val) ( ((buf)[0] = (uint8_t) (val) ) , \ + ((buf)[1] = (uint8_t) ((val)>>8) ) , \ + ((buf)[2] = (uint8_t) ((val)>>16) ) , \ + ((buf)[3] = (uint8_t) ((val)>>24) ) , \ + ((buf)[4] = (uint8_t) ((val)>>32) ) , \ + ((buf)[5] = (uint8_t) ((val)>>40) ) , \ + ((buf)[6] = (uint8_t) ((val)>>48) ) , \ + ((buf)[7] = (uint8_t) ((val)>>56) ) ) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) (REG) + +#define TOGGLE_BIT(REG, BIT) ((REG) ^= (BIT)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), ((READ_REG(REG) & (~(CLEARMASK))) | (SETMASK))) + +#define MODIFY_REG_FIELD(REG, FIELD_NAME, VAL) MODIFY_REG(REG, FIELD_NAME##_Msk, ((VAL)<<(FIELD_NAME##_Pos))&(FIELD_NAME##_Msk)) + +#define READ_REG_FIELD(REG, FIELD) ((REG & FIELD)>>FIELD##_Pos) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/* Use of interrupt control for register exclusive access (privileged mode only) */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + SET_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + CLEAR_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) + +/** + * @} + */ + +/**@brief TRUE, FALSE definition */ +#ifndef TRUE +#define TRUE ((BOOL)1U) +#endif +#ifndef FALSE +#define FALSE ((BOOL)0U) +#endif + +#if defined (USE_HAL_DRIVER) + #include "stm32wl3x_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WL3x_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3xx.h b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3xx.h new file mode 100644 index 0000000000..1776cf0696 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3xx.h @@ -0,0 +1,12863 @@ +/** + ****************************************************************************** + * @file stm32wl3xx.h + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32wl33 devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32WL3XX_H +#define STM32WL3XX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32WL3x + * @{ + */ + + + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ======================================== STM32WL3x Specific Interrupt Numbers =========================================== */ + FLASH_IRQn = 0, /*!< 0 NVM interrupt */ + RCC_IRQn = 1, /*!< 1 RCC interrupt */ + PVD_IRQn = 2, /*!< 2 PVD interrupt */ + I2C1_IRQn = 3, /*!< 3 I2C1 interrupt */ + I2C2_IRQn = 4, /*!< 4 I2C2 interrupt */ + SPI1_IRQn = 5, /*!< 5 SPI1 interrupt */ + SPI3_IRQn = 7, /*!< 7 SPI3 interrupt */ + USART1_IRQn = 8, /*!< 8 USART interrupt */ + LPUART1_IRQn = 9, /*!< 9 Low Power UART interrupt */ + TIM2_IRQn = 10, /*!< 10 Timer 2 interrupt */ + RTC_IRQn = 11, /*!< 11 RTC interrupt */ + ADC_IRQn = 12, /*!< 12 ADC interrupt */ + AES_IRQn = 13, /*!< 13 AES interrupt */ + GPIOA_IRQn = 15, /*!< 15 GPIOA interrupt */ + GPIOB_IRQn = 16, /*!< 16 GPIOB interrupt */ + DMA_IRQn = 17, /*!< 17 DMA interrupt */ + LPAWUR_IRQn = 18, /*!< 18 LPAWUR interrupt */ + COMP1_IRQn = 19, /*!< 19 Comp interrupt through SYSCFGBLE */ + MRSUBG_BUSY_IRQn = 20, /*!< 20 MR_SUBG Busy interrupt */ + MRSUBG_IRQn = 21, /*!< 21 MR_SUBG interrupt */ + MRSUBG_TX_RX_SEQUENCE_IRQn = 22, /*!< 22 MR_SUBG TX/RX Sequence interrupt */ + MRSUBG_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 CPU Wakeup interrupt */ + MRSUBG_WKUP_IRQn = 24, /*!< 24 SUBG Wakeup interrupt */ + DAC_IRQn = 25, /*!< 25 DAC interrupt */ + TIM16_IRQn = 26, /*!< 26 TIM16 interrupt */ + LCD_IRQn = 27, /*!< 27 LCD interrupt */ + LCSC_IRQn = 28, /*!< 28 LCSC interrupt */ + LCSC_LC_ACTIVITY_IRQn = 29 /*!< 28 LCSC LC activity interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +/** @addtogroup Configuration_of_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< CM0PLUS Core Revision r0p1 */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Vector Table Offset Register supported */ +#define __MPU_PRESENT 1 /*!< M0+ provides an MPU */ +#define __FPU_PRESENT 0 /*!< FPU not present */ +/** + * @} + */ + + + /*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x40001014U) /*!< Package size data register base address */ +#define UID64_BASE ((uint32_t)0x10001EF0U) /*!< 64-bit Unique device Identification */ +#define FLASHSIZE_BASE ((uint32_t)0x40001014U) /*!< Flash size data register base address */ +#define RAMSIZE_BASE ((uint32_t)0x40001014U) /*!< RAM size data register base address */ +#define DEV_ID_BASE ((uint32_t)0x40000000U) /*!< Device version and cut version register base address */ + + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_stm32wl3x.h" /*!< system_stm32wl3x macros and typedefs System util */ + + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access controller (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IO uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + __IO uint32_t IFCR; /*!< (@ 0x00000004) Interrupt flag clear register */ +} DMA_TypeDef; + +typedef struct { + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ + __IO uint32_t RESERVED; +} DMA_Channel_TypeDef; + + + + +/* =========================================================================================================================== */ +/* ================ DMAMUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access Multiplexer (DMAMUX) + */ + +/** + * @brief DMA Multiplexer + */ +typedef struct { /*!< DMAMUX Structure */ + __IO uint32_t CxCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +} DMAMUX_Channel_TypeDef; + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cyclic redundancy check calculation unit (CRC) + */ + +typedef struct { /*!< CRC Structure */ + __IO uint32_t DR; /*!< (@ 0x00000000) Data register */ + __IO uint32_t IDR; /*!< (@ 0x00000004) Independent data register */ + __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ + __IO uint32_t RESERVED; + __IO uint32_t INIT; /*!< (@ 0x00000010) Initial CRC value */ + __IO uint32_t POL; /*!< (@ 0x00000014) Polynomial */ +} CRC_TypeDef; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Independent watchdog (IWDG) + */ + +typedef struct { /*!< IWDG Structure */ + __IO uint32_t KR; /*!< (@ 0x00000000) Key register */ + __IO uint32_t PR; /*!< (@ 0x00000004) Prescaler register */ + __IO uint32_t RLR; /*!< (@ 0x00000008) Reload register */ + __IO uint32_t SR; /*!< (@ 0x0000000C) Status register */ + __IO uint32_t WINR; /*!< (@ 0x00000010) Window register */ +} IWDG_TypeDef; /*!< Size = 20 (0x14) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-integrated circuit (I2C) + */ + +typedef struct { /*!< I2C1 Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t OAR1; /*!< (@ 0x00000008) Own address register 1 */ + __IO uint32_t OAR2; /*!< (@ 0x0000000C) Own address register 2 */ + __IO uint32_t TIMINGR; /*!< (@ 0x00000010) Timing register */ + __IO uint32_t TIMEOUTR; /*!< (@ 0x00000014) Timeout register */ + __IO uint32_t ISR; /*!< (@ 0x00000018) Interrupt and Status register */ + __IO uint32_t ICR; /*!< (@ 0x0000001C) Interrupt clear register */ + __IO uint32_t PECR; /*!< (@ 0x00000020) PEC register */ + __IO uint32_t RXDR; /*!< (@ 0x00000024) Receive data register */ + __IO uint32_t TXDR; /*!< (@ 0x00000028) Transmit data register */ +} I2C_TypeDef; /*!< Size = 44 (0x2C) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH (FLASH) + */ + +typedef struct { /*!< FLASH Structure */ + __IO uint32_t COMMAND; /*!< (@ 0x00000000) Command register */ + __IO uint32_t CONFIG; /*!< (@ 0x00000004) Configuration register */ + __IO uint32_t IRQSTAT; /*!< (@ 0x00000008) Interrupt status register */ + __IO uint32_t IRQMASK; /*!< (@ 0x0000000C) Interrupt mask register */ + __IO uint32_t IRQRAW; /*!< (@ 0x00000010) Intertupt raw status register */ + __IO uint32_t SIZE; /*!< (@ 0x00000014) SIZE register */ + __IO uint32_t ADDRESS; /*!< (@ 0x00000018) Address register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t LFSRVAL; /*!< (@ 0x00000024) LFSRVAL register */ + __IO uint32_t RESERVED2[3]; + __IO uint32_t PAGEPROT0; /*!< (@ 0x00000034) Main Flash page protection register 0 */ + __IO uint32_t PAGEPROT1; /*!< (@ 0x00000038) Main Flash page protection register 1 */ + __IO uint32_t RESERVED1; + __IO uint32_t DATA0; /*!< (@ 0x00000040) Data register 0 */ + __IO uint32_t DATA1; /*!< (@ 0x00000044) Data register 1 */ + __IO uint32_t DATA2; /*!< (@ 0x00000048) Data register 2 */ + __IO uint32_t DATA3; /*!< (@ 0x0000004C) Data register 3 */ +} FLASH_TypeDef; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial peripheral interface/Inter-IC sound (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t SR; /*!< (@ 0x00000008) Status register */ + __IO uint32_t DR; /*!< (@ 0x0000000C) Data register */ + __IO uint32_t CRCPR; /*!< (@ 0x00000010) CRC polynomial register */ + __IO uint32_t RXCRCR; /*!< (@ 0x00000014) RX CRC register */ + __IO uint32_t TXCRCR; /*!< (@ 0x00000018) TX CRC register */ + __IO uint32_t I2SCFGR; /*!< (@ 0x0000001C) I2S configuration register */ + __IO uint32_t I2SPR; /*!< (@ 0x00000020) I2S prescaler register */ +} SPI_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ RCC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Reset and clock control (RCC) + */ + +typedef struct{ /*!< RCC Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) CR register */ + __IO uint32_t ICSCR; /*!< (@ 0x00000004) ICSCR register */ + __IO uint32_t CFGR; /*!< (@ 0x00000008) CFGR register */ + __IO uint32_t CSSWCR; /*!< (@ 0x0000000C) CSSWCR register */ + __IO uint32_t KRMR; /*!< (@ 0x00000010) KRMR register */ + __IO uint32_t RESERVED; + __IO uint32_t CIER; /*!< (@ 0x00000018) CIER register */ + __IO uint32_t CIFR; /*!< (@ 0x0000001C) CIFR register */ + __IO uint32_t CSCMDR; /*!< (@ 0x00000020) CSCMDR register */ + __IO uint32_t RESERVED1[3]; + __IO uint32_t AHBRSTR; /*!< (@ 0x00000030) AHBRSTR register */ + __IO uint32_t APB0RSTR; /*!< (@ 0x00000034) APB0RSTR register */ + __IO uint32_t APB1RSTR; /*!< (@ 0x00000038) APB1RSTR register */ + __IO uint32_t RESERVED2; + __IO uint32_t APB2RSTR; /*!< (@ 0x00000040) APB2RSTR register */ + __IO uint32_t RESERVED3[3]; + __IO uint32_t AHBENR; /*!< (@ 0x00000050) AHBENR register */ + __IO uint32_t APB0ENR; /*!< (@ 0x00000054) APB0ENR register */ + __IO uint32_t APB1ENR; /*!< (@ 0x00000058) APB1ENR register */ + __IO uint32_t RESERVED4; + __IO uint32_t APB2ENR; /*!< (@ 0x00000060) APB2ENR register */ + __IO uint32_t RESERVED5[12]; + __IO uint32_t CSR; /*!< (@ 0x00000094) CSR register */ + __IO uint32_t RFSWHSECR;/*!< (@ 0x00000098) RFSWHSECR register */ + __IO uint32_t RFHSECR; /*!< (@ 0x0000009C) RFHSECR register */ + __IO uint32_t AHBSMENR; /*!< (@ 0x000000A0) AHBSMENR register */ + __IO uint32_t APB0SMENR;/*!< (@ 0x000000A4) APB0SMENR register */ + __IO uint32_t APB1SMENR;/*!< (@ 0x000000A8) APB1SMENR register */ +} RCC_TypeDef; /*!< Size = 172 (0xAC) */ + + + +/* =========================================================================================================================== */ +/* ================ PWR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (PWR) + */ + +typedef struct{ /*!< PWR Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) CR1 register */ + __IO uint32_t CR2; /*!< (@ 0x00000004) CR2 register */ + __IO uint32_t IEWU; /*!< (@ 0x00000008) IEWU register */ + __IO uint32_t IWUP; /*!< (@ 0x0000000C) IWUP register */ + __IO uint32_t IWUF; /*!< (@ 0x00000010) IWUF register */ + __IO uint32_t SR2; /*!< (@ 0x00000014) SR2 register */ + __IO uint32_t RESERVED; + __IO uint32_t CR5; /*!< (@ 0x0000001C) CR5 register */ + __IO uint32_t PUCRA; /*!< (@ 0x00000020) PUCRA register */ + __IO uint32_t PDCRA; /*!< (@ 0x00000024) PDCRA register */ + __IO uint32_t PUCRB; /*!< (@ 0x00000028) PUCRB register */ + __IO uint32_t PDCRB; /*!< (@ 0x0000002C) PDCRB register */ + __IO uint32_t EWUA; /*!< (@ 0x00000030) EWUA register */ + __IO uint32_t WUPA; /*!< (@ 0x00000034) WUPA register */ + __IO uint32_t WUFA; /*!< (@ 0x00000038) WUFA register */ + __IO uint32_t RESERVED1; + __IO uint32_t EWUB; /*!< (@ 0x00000040) EWUB register */ + __IO uint32_t WUPB; /*!< (@ 0x00000044) WUPB register */ + __IO uint32_t WUFB; /*!< (@ 0x00000048) WUFB register */ + __IO uint32_t SDWN_WUEN; /*!< (@ 0x0000004C) SDWN_WUEN register */ + __IO uint32_t SDWN_WUPOL;/*!< (@ 0x00000050) SDWN_WUPOL register */ + __IO uint32_t SDWN_WUF; /*!< (@ 0x00000054) SDWN_WUF register */ + __IO uint32_t BOF_TUNE; /*!< (@ 0x00000058) BOF_TUNE register */ + __IO uint32_t RESERVED2[10]; + __IO uint32_t DBGR; /*!< (@ 0x00000084) DBGR register */ + __IO uint32_t EXTSRR; /*!< (@ 0x00000088) EXTSRR register */ + __IO uint32_t RESERVED3; + __IO uint32_t TRIMR; /*!< (@ 0x00000090) TRIMR register */ + __IO uint32_t ENGTRIM; /*!< (@ 0x00000094) ENGTRIM register */ + __IO uint32_t RESERVED4[2]; + __IO uint32_t ENGTRIM2; /*!< (@ 0x000000A0) ENGTRIM register */ +} PWR_TypeDef; /*!< Size = 164 (0xA4) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System configuration controller (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IO uint32_t DIE_ID; /*!< (@ 0x00000000) Die ID register */ + __IO uint32_t JTAG_ID; /*!< (@ 0x00000004) JTAG ID register */ + __IO uint32_t I2C_FMP_CTRL; /*!< (@ 0x00000008) I2C Fast-Mode Plus pin capability control register */ + __IO uint32_t IO_DTR; /*!< (@ 0x0000000C) I/O Interrupt detection type register */ + __IO uint32_t IO_IBER; /*!< (@ 0x00000010) I/O Interrupt Edge register */ + __IO uint32_t IO_IEVR; /*!< (@ 0x00000014) I/O Interrupt polarity event register */ + __IO uint32_t IO_IER; /*!< (@ 0x00000018) I/O Interrupt Enable register */ + __IO uint32_t IO_ISCR; /*!< (@ 0x0000001C) I/O Interrupt Status and Clear register */ + __IO uint32_t PWRC_IER; /*!< (@ 0x00000020) Power Controller Interrupt Enable register */ + __IO uint32_t PWRC_ISCR; /*!< (@ 0x00000024) Power Controller Interrupt Status and Clear register */ + __IO uint32_t GPIO_SWA_CTRL; /*!< (@ 0x00000028) I/O analog switch control register */ + __IO uint32_t INTAI_DTR; /*!< (@ 0x0000002C) Internal asynchronous interrupt detection type register */ + __IO uint32_t INTAI_IBER; /*!< (@ 0x00000030) Internal asynchronous interrupt edge register */ + __IO uint32_t INTAI_IEVR; /*!< (@ 0x00000034) Internal asynchronous interrupt polarity event register */ + __IO uint32_t INTAI_IER; /*!< (@ 0x00000038) Internal asynchronous interrupt enable register */ + __IO uint32_t INTAI_ISCR; /*!< (@ 0x0000003C) Internal asynchronous interrupt detection status and clear register */ + __IO uint32_t SR1; /*!< (@ 0x00000040) SYSCFG status register 1 */ +} SYSCFG_TypeDef; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random number generator (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t SR; /*!< (@ 0x00000004) Status register */ + __IO uint32_t VAL; /*!< (@ 0x00000008) Data register */ +} RNG_TypeDef; /*!< Size = 12 (0xC) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General-purpose I/Os (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __IO uint32_t MODER; /*!< (@ 0x00000000) GPIO port mode register */ + __IO uint32_t OTYPER; /*!< (@ 0x00000004) GPIO port output type register */ + __IO uint32_t OSPEEDR; /*!< (@ 0x00000008) GPIO port output speed register */ + __IO uint32_t PUPDR; /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register */ + __IO uint32_t IDR; /*!< (@ 0x00000010) GPIO port input data register */ + __IO uint32_t ODR; /*!< (@ 0x00000014) GPIO port output data register */ + __IO uint32_t BSRR; /*!< (@ 0x00000018) GPIO port bit set/reset register */ + __IO uint32_t LCKR; /*!< (@ 0x0000001C) GPIO port configuration lock register */ + __IO uint32_t AFR[2]; /*!< (@ 0x00000020) GPIO alternate function register */ + __IO uint32_t BRR; /*!< (@ 0x00000028) GPIO bit reset register */ +} GPIO_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ TIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Advanced-timers (TIM) + */ + +typedef struct { /*!< TIMx Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t SMCR; /*!< (@ 0x00000008) Slave mode control register */ + __IO uint32_t DIER; /*!< (@ 0x0000000C) DMA/Interrupt enable register */ + __IO uint32_t SR; /*!< (@ 0x00000010) Status register */ + __IO uint32_t EGR; /*!< (@ 0x00000014) Event generation register */ + __IO uint32_t CCMR1; /*!< (@ 0x00000018) Input capture and output compare mode register 1 */ + __IO uint32_t CCMR2; /*!< (@ 0x0000001C) Input capture and output compare mode register 2 */ + __IO uint32_t CCER; /*!< (@ 0x00000020) Capture/compare enable register */ + __IO uint32_t CNT; /*!< (@ 0x00000024) Counter */ + __IO uint32_t PSC; /*!< (@ 0x00000028) Prescaler */ + __IO uint32_t ARR; /*!< (@ 0x0000002C) Auto-reload register */ + __IO uint32_t RCR; /*!< (@ 0x00000030) Repetition counter register */ + __IO uint32_t CCR1; /*!< (@ 0x00000034) Capture/compare register 1 */ + __IO uint32_t CCR2; /*!< (@ 0x00000038) Capture/compare register 2 */ + __IO uint32_t CCR3; /*!< (@ 0x0000003C) Capture/compare register 3 */ + __IO uint32_t CCR4; /*!< (@ 0x00000040) Capture/compare register 4 */ + __IO uint32_t BDTR; /*!< (@ 0x00000044) Break and dead-time register */ + __IO uint32_t DCR; /*!< (@ 0x00000048) DMA control register */ + __IO uint32_t DMAR; /*!< (@ 0x0000004C) DMA address for full transfer */ + __IO uint32_t OR; /*!< (@ 0x00000050) Option register 1 */ + __IO uint32_t RESERVED[3]; + __IO uint32_t AF1; /*!< (@ 0x00000060) TIM alternate function option register 1 */ + __IO uint32_t RESERVED1; + __IO uint32_t TISEL; /*!< (@ 0x00000068) Input selection register */ +} TIM_TypeDef; /*!< Size = 108 (0x6C) */ + + + +/* =========================================================================================================================== */ +/* ================ USART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal synchronous asynchronous receiver transmitter (USART) + */ + +typedef struct { /*!< USART Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t CR3; /*!< (@ 0x00000008) Control register 3 */ + __IO uint32_t BRR; /*!< (@ 0x0000000C) Baud rate register */ + __IO uint32_t GTPR; /*!< (@ 0x00000010) Guard time and prescaler register */ + __IO uint32_t RTOR; /*!< (@ 0x00000014) Receiver timeout register */ + __IO uint32_t RQR; /*!< (@ 0x00000018) Request register */ + __IO uint32_t ISR; /*!< (@ 0x0000001C) Interrupt & status register */ + __IO uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + __IO uint32_t RDR; /*!< (@ 0x00000024) Receive data register */ + __IO uint32_t TDR; /*!< (@ 0x00000028) Transmit data register */ + __IO uint32_t PRESC; /*!< (@ 0x0000002C) Prescaler register */ +} USART_TypeDef; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time clock (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IO uint32_t TR; /*!< (@ 0x00000000) Time register */ + __IO uint32_t DR; /*!< (@ 0x00000004) Date register */ + __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ + __IO uint32_t ISR; /*!< (@ 0x0000000C) Initialization and status register */ + __IO uint32_t PRER; /*!< (@ 0x00000010) Prescaler register */ + __IO uint32_t WUTR; /*!< (@ 0x00000014) Wakeup timer register */ + __IO uint32_t RESERVED; + __IO uint32_t ALRMAR; /*!< (@ 0x0000001C) Alarm A register */ + __IO uint32_t RESERVED1; + __IO uint32_t WPR; /*!< (@ 0x00000024) Write protection register */ + __IO uint32_t SSR; /*!< (@ 0x00000028) Sub second register */ + __IO uint32_t SHIFTR; /*!< (@ 0x0000002C) Shift control register */ + __IO uint32_t TSTR; /*!< (@ 0x00000030) Timestamp time register */ + __IO uint32_t TSDR; /*!< (@ 0x00000034) Timestamp date register */ + __IO uint32_t TSSSR; /*!< (@ 0x00000038) Timestamp sub second register */ + __IO uint32_t CALR; /*!< (@ 0x0000003C) Calibration register */ + __IO uint32_t TAMPCR; /*!< (@ 0x00000040) Tamper configuration register */ + __IO uint32_t ALRMASSR; /*!< (@ 0x00000044) Alarm A sub second register */ + __IO uint32_t RESERVED2; + __IO uint32_t OR; /*!< (@ 0x0000004C) Option register */ + __IO uint32_t BKP0R; /*!< (@ 0x00000050) Backup register 0 */ + __IO uint32_t BKP1R; /*!< (@ 0x00000054) Backup register 1 */ +} RTC_TypeDef; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ AES ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Advanced encryption standard hardware accelerator (AES) + */ + +typedef struct { /*!< AES Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control Register */ + __IO uint32_t SR; /*!< (@ 0x00000004) Status Register */ + __IO uint32_t DINR; /*!< (@ 0x00000008) Data Input register */ + __IO uint32_t DOUTR; /*!< (@ 0x0000000C) Data Output register */ + __IO uint32_t KEYR0; /*!< (@ 0x00000010) Key register 0 */ + __IO uint32_t KEYR1; /*!< (@ 0x00000014) Key register 1 */ + __IO uint32_t KEYR2; /*!< (@ 0x00000018) Key register 2 */ + __IO uint32_t KEYR3; /*!< (@ 0x0000001C) Key register 3 */ + __IO uint32_t IVR0; /*!< (@ 0x00000020) Initialization vector register 0 */ + __IO uint32_t IVR1; /*!< (@ 0x00000024) Initialization vector register 1 */ + __IO uint32_t IVR2; /*!< (@ 0x00000028) Initialization vector register 2 */ + __IO uint32_t IVR3; /*!< (@ 0x0000002C) Initialization vector register 3 */ + __IO uint32_t KEYR4; /*!< (@ 0x00000030) Key register 4 */ + __IO uint32_t KEYR5; /*!< (@ 0x00000034) Key register 5 */ + __IO uint32_t KEYR6; /*!< (@ 0x00000038) Key register 6 */ + __IO uint32_t KEYR7; /*!< (@ 0x0000003C) Key register 7 */ + __IO uint32_t SUSP0; /*!< (@ 0x00000040) Suspend register 0 */ + __IO uint32_t SUSP1; /*!< (@ 0x00000044) Suspend register 1 */ + __IO uint32_t SUSP2; /*!< (@ 0x00000048) Suspend register 2 */ + __IO uint32_t SUSP3; /*!< (@ 0x0000004C) Suspend register 3 */ + __IO uint32_t SUSP4; /*!< (@ 0x00000050) Suspend register 4 */ + __IO uint32_t SUSP5; /*!< (@ 0x00000054) Suspend register 5 */ + __IO uint32_t SUSP6; /*!< (@ 0x00000058) Suspend register 6 */ + __IO uint32_t SUSP7; /*!< (@ 0x0000005C) Suspend register 7 */ +} AES_TypeDef; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IO uint32_t VERSION_ID; /*!< (@ 0x00000000) VERSION_ID register */ + __IO uint32_t CONF; /*!< (@ 0x00000004) ADC configuration register */ + __IO uint32_t CTRL; /*!< (@ 0x00000008) ADC control register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t SWITCH; /*!< (@ 0x00000014) ADC switch control for Input Selection */ + __IO uint32_t RESERVED1; + __IO uint32_t DS_CONF; /*!< (@ 0x0000001C) Downsampler configuration register */ + __IO uint32_t SEQ_1; /*!< (@ 0x00000020) ADC regular sequence programming register 1 */ + __IO uint32_t SEQ_2; /*!< (@ 0x00000024) ADC regular sequence programming register 2 */ + __IO uint32_t COMP_1; /*!< (@ 0x00000028) ADC Gain & offset correction values register 1 */ + __IO uint32_t COMP_2; /*!< (@ 0x0000002C) ADC Gain & offset correction values register 2 */ + __IO uint32_t COMP_3; /*!< (@ 0x00000030) ADC Gain & offset correction values register 3 */ + __IO uint32_t COMP_4; /*!< (@ 0x00000034) ADC Gain & offset correction values register 4 */ + __IO uint32_t COMP_SEL; /*!< (@ 0x00000038) ADC Gain & Offset selection values register */ + __IO uint32_t WD_TH; /*!< (@ 0x0000003C) ADC watchdog threshold register register */ + __IO uint32_t WD_CONF; /*!< (@ 0x00000040) ADC watchdog configuration register */ + __IO uint32_t DS_DATAOUT; /*!< (@ 0x00000044) Downsampler Data output register */ + __IO uint32_t RESERVED2; + __IO uint32_t IRQ_STATUS; /*!< (@ 0x0000004C) Interrupt Status register */ + __IO uint32_t IRQ_ENABLE; /*!< (@ 0x00000050) Enable/disable Interrupts */ +} ADC_TypeDef; /*!< Size = 84 (0x54) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< COMP Structure */ + __IO uint32_t CSR; /*!< (@ 0x00000000) Control and status register */ +} COMP_TypeDef; /*!< Size = 4 (0x04) */ + + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Digital to Analog Converter (DAC) + */ + +typedef struct { /*!< DAC Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t SWTRIGR; /*!< (@ 0x00000004) Software trigger register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t DHR; /*!< (@ 0x00000010) Channel data holding register */ + __IO uint32_t RESERVED1[6]; + __IO uint32_t DOR; /*!< (@ 0x0000002C) Channel data output register */ + __IO uint32_t RESERVED2; + __IO uint32_t SR; /*!< (@ 0x00000034) Status register */ +} DAC_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ LCSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LC Sensor Controller (LCSC) + */ + +typedef struct{ /*!< LCSC Structure */ + __IO uint32_t CR0; /*!< (@ 0x00000000) LCSC_CR0 register */ + __IO uint32_t CR1; /*!< (@ 0x00000004) LCSC_CR1 register */ + __IO uint32_t CR2; /*!< (@ 0x00000008) LCSC_CR2 register */ + __IO uint32_t PULSE_CR; /*!< (@ 0x0000000C) LCSC_PULSE_CR register */ + __IO uint32_t ENR; /*!< (@ 0x00000010) LCSC_ENR register */ + __IO uint32_t WHEEL_SR; /*!< (@ 0x00000014) LCSC_WHEEL_SR register */ + __IO uint32_t CONFR; /*!< (@ 0x00000018) LCSC_CONFR register */ + __IO uint32_t COMP_CTN; /*!< (@ 0x0000001C) LCSC_COMP_CTN register */ + __IO uint32_t SR; /*!< (@ 0x00000020) LCSC_SR register */ + __IO uint32_t STAT; /*!< (@ 0x00000024) LCSC_STAT register */ + __IO uint32_t RESERVED[6]; + __IO uint32_t VER; /*!< (@ 0x00000040) LCSC_VER register */ + __IO uint32_t ISR; /*!< (@ 0x00000044) LCSC_ISR register */ +} LCSC_TypeDef; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ DBGMCU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU debug component (DBGMCU) + */ + +typedef struct{ /*!< DBGMCU Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) CR register */ + __IO uint32_t DBG_APB0_FZ; /*!< (@ 0x00000004) DBG_APB0_FZ register */ + __IO uint32_t DBG_APB1_FZ; /*!< (@ 0x00000008) DBG_APB1_FZ register */ +} DBGMCU_TypeDef; /*!< Size = 12 (0x0C) */ + + + +/* =========================================================================================================================== */ +/* ================ LCD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Liquid crystal display controller (LCD) + */ + +typedef struct { /*!< LCD Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t FCR; /*!< (@ 0x00000004) Frame control register */ + __IO uint32_t SR; /*!< (@ 0x00000008) Status register */ + __IO uint32_t CLR; /*!< (@ 0x0000000C) Clear register */ + __IO uint32_t RESERVED; + __IO uint32_t RAM_COM0; /*!< (@ 0x00000014) Disaplay Memory COM 0 */ + __IO uint32_t RESERVED1; + __IO uint32_t RAM_COM1; /*!< (@ 0x0000001C) Disaplay Memory COM 1 */ + __IO uint32_t RESERVED2; + __IO uint32_t RAM_COM2; /*!< (@ 0x00000024) Disaplay Memory COM 2 */ + __IO uint32_t RESERVED3; + __IO uint32_t RAM_COM3; /*!< (@ 0x0000002C) Disaplay Memory COM 3 */ + __IO uint32_t RESERVED4; + __IO uint32_t RAM_COM4; /*!< (@ 0x00000034) Disaplay Memory COM 4 */ + __IO uint32_t RESERVED5; + __IO uint32_t RAM_COM5; /*!< (@ 0x0000003C) Disaplay Memory COM 5 */ + __IO uint32_t RESERVED6; + __IO uint32_t RAM_COM6; /*!< (@ 0x00000044) Disaplay Memory COM 6 */ + __IO uint32_t RESERVED7; + __IO uint32_t RAM_COM7; /*!< (@ 0x0000004C) Disaplay Memory COM 7 */ +} LCD_TypeDef; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Radio + */ + +typedef struct{ /*!< MR_SUBG_RADIO Structure */ + __IO uint32_t RF_FSM0_TIMEOUT; /*!< (@ 0x00000000) RF_FSM0_TIMEOUT register */ + __IO uint32_t RF_FSM1_TIMEOUT; /*!< (@ 0x00000004) RF_FSM1_TIMEOUT register */ + __IO uint32_t RF_FSM2_TIMEOUT; /*!< (@ 0x00000008) RF_FSM2_TIMEOUT register */ + __IO uint32_t RF_FSM3_TIMEOUT; /*!< (@ 0x0000000C) RF_FSM3_TIMEOUT register */ + __IO uint32_t RF_FSM4_TIMEOUT; /*!< (@ 0x00000010) RF_FSM4_TIMEOUT register */ + __IO uint32_t RF_FSM5_TIMEOUT; /*!< (@ 0x00000014) RF_FSM5_TIMEOUT register */ + __IO uint32_t RF_FSM6_TIMEOUT; /*!< (@ 0x00000018) RF_FSM6_TIMEOUT register */ + __IO uint32_t RF_FSM7_TIMEOUT; /*!< (@ 0x0000001C) RF_FSM7_TIMEOUT register */ + __IO uint32_t AFC0_CONFIG; /*!< (@ 0x00000020) AFC0_CONFIG register */ + __IO uint32_t AFC1_CONFIG; /*!< (@ 0x00000024) AFC1_CONFIG register */ + __IO uint32_t AFC2_CONFIG; /*!< (@ 0x00000028) AFC2_CONFIG register */ + __IO uint32_t AFC3_CONFIG; /*!< (@ 0x0000002C) AFC3_CONFIG register */ + __IO uint32_t CLKREC_CTRL0; /*!< (@ 0x00000030) CLKREC_CTRL0 register */ + __IO uint32_t CLKREC_CTRL1; /*!< (@ 0x00000034) CLKREC_CTRL1 register */ + __IO uint32_t DCREM_CTRL0; /*!< (@ 0x00000038) DCREM_CTRL0 register */ + __IO uint32_t DCREM_CTRL1; /*!< (@ 0x0000003C) DCREM_CTRL1 register */ + __IO uint32_t IQC_CTRL0; /*!< (@ 0x00000040) IQC_CTRL0 register */ + __IO uint32_t IQC_CTRL1; /*!< (@ 0x00000044) IQC_CTRL1 register */ + __IO uint32_t IQC_CTRL2; /*!< (@ 0x00000048) IQC_CTRL2 register */ + __IO uint32_t IQC_CTRL3; /*!< (@ 0x0000004C) IQC_CTRL3 register */ + __IO uint32_t RESERVED; + __IO uint32_t AGC0_CTRL; /*!< (@ 0x00000054) AGC0_CTRL register */ + __IO uint32_t AGC1_CTRL; /*!< (@ 0x00000058) AGC1_CTRL register */ + __IO uint32_t AGC2_CTRL; /*!< (@ 0x0000005C) AGC2_CTRL register */ + __IO uint32_t AGC3_CTRL; /*!< (@ 0x00000060) AGC3_CTRL register */ + __IO uint32_t AGC4_CTRL; /*!< (@ 0x00000064) AGC4_CTRL register */ + __IO uint32_t AGC_ATTEN0; /*!< (@ 0x00000068) AGC_ATTEN0 register */ + __IO uint32_t AGC_ATTEN1; /*!< (@ 0x0000006C) AGC_ATTEN1 register */ + __IO uint32_t AGC_ATTEN2; /*!< (@ 0x00000070) AGC_ATTEN2 register */ + __IO uint32_t AGC_ATTEN3; /*!< (@ 0x00000074) AGC_ATTEN3 register */ + __IO uint32_t AGC_ATTEN4; /*!< (@ 0x00000078) AGC_ATTEN4 register */ + __IO uint32_t AGC_ATTEN5; /*!< (@ 0x0000007C) AGC_ATTEN5 register */ + __IO uint32_t AGC_ATTEN6; /*!< (@ 0x00000080) AGC_ATTEN6 register */ + __IO uint32_t AGC_ATTEN7; /*!< (@ 0x00000084) AGC_ATTEN7 register */ + __IO uint32_t AGC_ATTEN8; /*!< (@ 0x00000088) AGC_ATTEN8 register */ + __IO uint32_t AGC_ATTEN9; /*!< (@ 0x0000008C) AGC_ATTEN9 register */ + __IO uint32_t AGC1_ATTEN_TRIM; /*!< (@ 0x00000090) AGC1_ATTEN_TRIM register */ + __IO uint32_t AGC2_ATTEN_TRIM; /*!< (@ 0x00000094) AGC2_ATTEN_TRIM register */ + __IO uint32_t AGC3_ATTEN_TRIM; /*!< (@ 0x00000098) AGC3_ATTEN_TRIM register */ + __IO uint32_t AGC4_ATTEN_TRIM; /*!< (@ 0x0000009C) AGC4_ATTEN_TRIM register */ + __IO uint32_t AGC_PGA_HWTRIM_OUT; /*!< (@ 0x000000A0) AGC_PGA_HWTRIM_OUT register */ + __IO uint32_t RESERVED1; + __IO uint32_t PA_REG; /*!< (@ 0x000000A8) PA_REG register */ + __IO uint32_t PA_HWTRIM_OUT; /*!< (@ 0x000000AC) PA_HWTRIM_OUT register */ + __IO uint32_t RESERVED2[3]; + __IO uint32_t RSSI_FLT; /*!< (@ 0x000000BC) RSSI_FLT register */ + __IO uint32_t RESERVED3[2]; + __IO uint32_t SYNTH2_ANA_ENG; /*!< (@ 0x000000C8) SYNTH2_ANA_ENG register */ + __IO uint32_t RESERVED4[7]; + __IO uint32_t RXADC_HWDELAYTRIM_OUT; /*!< (@ 0x000000E8) RXADC_HWDELAYTRIM_OUT register */ + __IO uint32_t RESERVED5[2]; + __IO uint32_t RX_AAF_HWTRIM_OUT; /*!< (@ 0x000000F4) RX_AAF_HWTRIM_OUT register */ + __IO uint32_t RESERVED6[2]; + __IO uint32_t SINGEN_ANA_ENG; /*!< (@ 0x00000100) SINGEN_ANA_ENG register */ + __IO uint32_t RESERVED7; + __IO uint32_t RF_INFO_OUT; /*!< (@ 0x00000108) RF_INFO_OUT register */ + __IO uint32_t RESERVED8[6]; + __IO uint32_t RF_FSM8_TIMEOUT; /*!< (@ 0x00000124) RF_FSM8_TIMEOUT register */ + __IO uint32_t RF_FSM9_TIMEOUT; /*!< (@ 0x00000128) RF_FSM9_TIMEOUT register */ + __IO uint32_t RF_FSM10_TIMEOUT; /*!< (@ 0x0000012C) RF_FSM10_TIMEOUT register */ + __IO uint32_t RESERVED9[5]; + __IO uint32_t SUBG_DIG_CTRL0; /*!< (@ 0x00000144) SUBG_DIG_CTRL0 register */ +} MR_SUBG_RADIO_TypeDef; /*!< Size = 328 (0x148) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_STATIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Static + */ + +typedef struct{ /*!< MR_SUBG_GLOB_STATIC Structure */ + __IO uint32_t PCKT_CONFIG; /*!< (@ 0x00000000) PCKT_CONFIG register */ + __IO uint32_t SYNC; /*!< (@ 0x00000004) SYNC register */ + __IO uint32_t SEC_SYNC; /*!< (@ 0x00000008) SEC_SYNC register */ + __IO uint32_t CRC_INIT; /*!< (@ 0x0000000C) CRC_INIT register */ + __IO uint32_t PCKT_CTRL; /*!< (@ 0x00000010) PCKT_CTRL register */ + __IO uint32_t DATABUFFER0_PTR; /*!< (@ 0x00000014) DATABUFFER0_PTR register */ + __IO uint32_t DATABUFFER1_PTR; /*!< (@ 0x00000018) DATABUFFER1_PTR register */ + __IO uint32_t DATABUFFER_SIZE; /*!< (@ 0x0000001C) DATABUFFER_SIZE register */ + __IO uint32_t PA_LEVEL_3_0; /*!< (@ 0x00000020) PA_LEVEL_3_0 register */ + __IO uint32_t PA_LEVEL_7_4; /*!< (@ 0x00000024) PA_LEVEL_7_4 register */ + __IO uint32_t PA_CONFIG; /*!< (@ 0x00000028) PA_CONFIG register */ + __IO uint32_t IF_CTRL; /*!< (@ 0x0000002C) IF_CTRL register */ + __IO uint32_t AS_QI_CTRL; /*!< (@ 0x00000030) AS_QI_CTRL register */ + __IO uint32_t IQC_CONFIG; /*!< (@ 0x00000034) IQC_CONFIG register */ + __IO uint32_t DSSS_CTRL; /*!< (@ 0x00000038) DSSS_CTRL register */ +} MR_SUBG_GLOB_STATIC_TypeDef; /*!< Size = 60 (0x3C) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_DYNAMIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Dynamic + */ + +typedef struct{ /*!< MR_SUBG_GLOB_DYNAMIC Structure */ + __IO uint32_t PCKTLEN_CONFIG; /*!< (@ 0x00000000) PCKTLEN_CONFIG register */ + __IO uint32_t MOD0_CONFIG; /*!< (@ 0x00000004) MOD0_CONFIG register */ + __IO uint32_t MOD1_CONFIG; /*!< (@ 0x00000008) MOD1_CONFIG register */ + __IO uint32_t SYNTH_FREQ; /*!< (@ 0x0000000C) SYNTH_FREQ register */ + __IO uint32_t VCO_CAL_CONFIG; /*!< (@ 0x00000010) VCO_CAL_CONFIG register */ + __IO uint32_t RX_TIMER; /*!< (@ 0x00000014) RX_TIMER register */ + __IO uint32_t DATABUFFER_THR; /*!< (@ 0x00000018) DATABUFFER_THR register */ + __IO uint32_t RFSEQ_IRQ_ENABLE; /*!< (@ 0x0000001C) RFSEQ_IRQ_ENABLE register */ + __IO uint32_t ADDITIONAL_CTRL; /*!< (@ 0x00000020) ADDITIONAL_CTRL register */ + __IO uint32_t FAST_RX_TIMER; /*!< (@ 0x00000024) FAST_RX_TIMER register */ + __IO uint32_t COMMAND; /*!< (@ 0x00000028) COMMAND register */ +} MR_SUBG_GLOB_DYNAMIC_TypeDef; /*!< Size = 44 (0x2C) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_STATUS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Status + */ + +typedef struct{ /*!< MR_SUBG_GLOB_STATUS Structure */ + __IO uint32_t RFSEQ_IRQ_STATUS; /*!< (@ 0x00000000) RFSEQ_IRQ_STATUS register */ + __IO uint32_t RFSEQ_STATUS_DETAIL; /*!< (@ 0x00000004) RFSEQ_STATUS_DETAIL register */ + __IO uint32_t RADIO_FSM_INFO; /*!< (@ 0x00000008) RADIO_FSM_INFO register */ + __IO uint32_t RX_INDICATOR; /*!< (@ 0x0000000C) RX_INDICATOR register */ + __IO uint32_t RX_INFO_REG; /*!< (@ 0x00000010) RX_INFO_REG register */ + __IO uint32_t RX_CRC_REG; /*!< (@ 0x00000014) RX_CRC_REG register */ + __IO uint32_t QI_INFO; /*!< (@ 0x00000018) QI_INFO register */ + __IO uint32_t DATABUFFER_INFO; /*!< (@ 0x0000001C) DATABUFFER_INFO register */ + __IO uint32_t TIME_CAPTURE; /*!< (@ 0x00000020) TIME_CAPTURE register */ + __IO uint32_t IQC_CORRECTION_OUT; /*!< (@ 0x00000024) IQC_CORRECTION_OUT register */ + __IO uint32_t PA_SAFEASK_OUT; /*!< (@ 0x00000028) PA_SAFEASK_OUT register */ + __IO uint32_t VCO_CALIB_OUT; /*!< (@ 0x0000002C) VCO_CALIB_OUT register */ + __IO uint32_t SEQ_INFO; /*!< (@ 0x00000030) SEQ_INFO register */ + __IO uint32_t SEQ_EVENT_STATUS; /*!< (@ 0x00000034) SEQ_EVENT_STATUS register */ +} MR_SUBG_GLOB_STATUS_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_MISC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Misc + */ + +typedef struct{ /*!< MR_SUBG_GLOB_MISC Structure */ + __IO uint32_t RFIP_VERSION; /*!< (@ 0x00000000) RFIP_VERSION register */ + __IO uint32_t RRM_UDRA_CTRL; /*!< (@ 0x00000004) RRM_UDRA_CTRL register */ + __IO uint32_t SEQUENCER_CTRL; /*!< (@ 0x00000008) SEQUENCER_CTRL register */ + __IO uint32_t ABSOLUTE_TIME; /*!< (@ 0x0000000C) ABSOLUTE_TIME register */ + __IO uint32_t SCM_COUNTER_VAL; /*!< (@ 0x00000010) SCM_COUNTER_VAL register */ + __IO uint32_t SCM_MIN_MAX; /*!< (@ 0x00000014) SCM_MIN_MAX register */ + __IO uint32_t WAKEUP_IRQ_STATUS; /*!< (@ 0x00000018) WAKEUP_IRQ_STATUS register */ +} MR_SUBG_GLOB_MISC_TypeDef; /*!< Size = 28 (0x1C) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_RETAINED ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Retained + */ + +typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */ + __IO uint32_t RFIP_WAKEUPTIME; /*!< (@ 0x00000000) RFIP_WAKEUPTIME register */ + __IO uint32_t CPU_WAKEUPTIME; /*!< (@ 0x00000004) CPU_WAKEUPTIME register */ + __IO uint32_t WAKEUP_CTRL; /*!< (@ 0x00000008) WAKEUP_CTRL register */ + __IO uint32_t RRM_CMDLIST_PTR; /*!< (@ 0x0000000C) RRM_CMDLIST_PTR register */ + __IO uint32_t SEQ_GLOBALTABLE_PTR; /*!< (@ 0x00000010) SEQ_GLOBALTABLE_PTR register */ +} MR_SUBG_GLOB_RETAINED_TypeDef; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ LPAWUR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low Power Autonomous Wakeup Radio IP + */ + +typedef struct{ /*!< LPAWUR Structure */ + __IO uint32_t FRAME_CONFIG0; /*!< (@ 0x00000000) FRAME_CONFIG0 register */ + __IO uint32_t FRAME_CONFIG1; /*!< (@ 0x00000004) FRAME_CONFIG1 register */ + __IO uint32_t FRAME_SYNC_CONFIG; /*!< (@ 0x00000008) FRAME_SYNC_CONFIG register */ + __IO uint32_t RFIP_CONFIG; /*!< (@ 0x0000000C) RFIP_CONFIG register */ + __IO uint32_t RF_CONFIG; /*!< (@ 0x00000010) RF_CONFIG register */ + __IO uint32_t AGC_CONFIG; /*!< (@ 0x00000014) AGC_CONFIG register */ + __IO uint32_t RESERVED; + __IO uint32_t PAYLOAD_0; /*!< (@ 0x0000001C) PAYLOAD_0 register */ + __IO uint32_t PAYLOAD_1; /*!< (@ 0x00000020) PAYLOAD_1 register */ + __IO uint32_t RESERVED1[7]; + __IO uint32_t RFIP_VERSION; /*!< (@ 0x00000040) RFIP_VERSION register */ + __IO uint32_t IRQ_ENABLE; /*!< (@ 0x00000044) IRQ_ENABLE register */ + __IO uint32_t STATUS; /*!< (@ 0x00000048) STATUS register */ +} LPAWUR_TypeDef; /*!< Size = 76 (0x4C) */ + + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ +#define FLASH_BASE (0x10040000UL) /*!< Main FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + + +/*!< System Memory, OTP bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x10000000UL) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ +#define OTP_AREA_BASE (0x10001800UL) /*!< OTP area : 1kB (0x10001800 – 0x10001BFF) */ + +#define SRAM0_BASE SRAM_BASE /*!< SRAM0 (16 KB) base address */ +#define SRAM1_BASE (SRAM_BASE + 0x00004000UL) /*!< SRAM1 (16 KB) base address */ + +/* End addresses */ +#define SRAM0_END_ADDR (0x20003FFFUL) /*!< RAM0 : 16KB (0x20000000 – 0x20003FFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< RAM1 : 16KB (0x20004000 – 0x20007FFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x100017FFUL) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ +#define OTP_AREA_END_ADDR (0x10001BFFUL) /*!< OTP area : 1KB (0x10001800 – 0x10001BFF) */ + +/*!< Peripheral memory map */ +#define APB0PERIPH_BASE PERIPH_BASE +#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000LU) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000LU) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000LU) + + +/*!< APB0 peripherals */ +#define SYSCFG_BASE (APB0PERIPH_BASE + 0x0000UL) +#define FLASH_R_BASE (APB0PERIPH_BASE + 0x1000UL) +#define TIM2_BASE (APB0PERIPH_BASE + 0x2000UL) +#define IWDG_BASE (APB0PERIPH_BASE + 0x3000UL) +#define RTC_BASE (APB0PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB0PERIPH_BASE + 0x5000UL) +#define DAC1_BASE (APB0PERIPH_BASE + 0x6000UL) +#define LCD_BASE (APB0PERIPH_BASE + 0x7000UL) +#define DBGMCU_BASE (APB0PERIPH_BASE + 0x8000UL) +#define COMP_BASE (APB0PERIPH_BASE + 0x9000UL) +#define LCSC_BASE (APB0PERIPH_BASE + 0xA000UL) + + +/*!< APB1 peripherals */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x0000UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB1PERIPH_BASE + 0x2000UL) +#define USART1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x5000UL) +#define ADC1_BASE (APB1PERIPH_BASE + 0x6000UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x7000UL) + +/*!< AHB peripherals */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x000000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x100000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x200000UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x400000UL) +#define PWR_BASE (AHBPERIPH_BASE + 0x500000UL) +#define RNG_BASE (AHBPERIPH_BASE + 0x600000UL) +#define DMA1_BASE (AHBPERIPH_BASE + 0x700000UL) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x800000UL) +#define AES_BASE (AHBPERIPH_BASE + 0x900000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) + +/*!< APB2 peripherals */ +#define MR_SUBG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define MR_SUBG_RADIO_BASE (MR_SUBG_BASE + 0x0000UL) +#define MR_SUBG_GLOB_STATIC_BASE (MR_SUBG_BASE + 0x0400UL) +#define MR_SUBG_GLOB_DYNAMIC_BASE (MR_SUBG_BASE + 0x0500UL) +#define MR_SUBG_GLOB_STATUS_BASE (MR_SUBG_BASE + 0x0600UL) +#define MR_SUBG_GLOB_MISC_BASE (MR_SUBG_BASE + 0x0700UL) +#define MR_SUBG_GLOB_RETAINED_BASE (MR_SUBG_BASE + 0x0780UL) +#define LPAWUR_BASE (APB2PERIPH_BASE + 0x1000UL) + + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + +/* Peripherals available on APB0 bus */ +#define SYSCFG ((SYSCFG_TypeDef*) SYSCFG_BASE) +#define FLASH ((FLASH_TypeDef*) FLASH_R_BASE) +#define TIM2 ((TIM_TypeDef*) TIM2_BASE) +#define IWDG ((IWDG_TypeDef*) IWDG_BASE) +#define RTC ((RTC_TypeDef*) RTC_BASE) +#define TIM16 ((TIM_TypeDef*) TIM16_BASE) +#define DAC1 ((DAC_TypeDef*) DAC1_BASE) +#define LCD ((LCD_TypeDef*) LCD_BASE) +#define DBGMCU ((DBGMCU_TypeDef*) DBGMCU_BASE) +#define COMP1 ((COMP_TypeDef*) COMP_BASE) +#define LCSC ((LCSC_TypeDef*) LCSC_BASE) + +/* Peripherals available on APB1 bus */ +#define I2C1 ((I2C_TypeDef*) I2C1_BASE) +#define I2C2 ((I2C_TypeDef*) I2C2_BASE) +#define SPI1 ((SPI_TypeDef*) SPI1_BASE) +#define USART1 ((USART_TypeDef*) USART1_BASE) +#define LPUART1 ((USART_TypeDef*) LPUART1_BASE) +#define ADC1 ((ADC_TypeDef*) ADC1_BASE) +#define SPI3 ((SPI_TypeDef*) SPI3_BASE) + +/* Peripherals available on AHB bus */ +#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define CRC ((CRC_TypeDef*) CRC_BASE) +#define RCC ((RCC_TypeDef*) RCC_BASE) +#define PWR ((PWR_TypeDef*) PWR_BASE) +#define RNG ((RNG_TypeDef*) RNG_BASE) +#define DMA1 ((DMA_TypeDef*) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define AES ((AES_TypeDef*) AES_BASE) + +/* Peripherals available on APB2 bus */ +#define MR_SUBG_RADIO ((MR_SUBG_RADIO_TypeDef*) MR_SUBG_RADIO_BASE) +#define MR_SUBG_GLOB_STATIC ((MR_SUBG_GLOB_STATIC_TypeDef*) MR_SUBG_GLOB_STATIC_BASE) +#define MR_SUBG_GLOB_DYNAMIC ((MR_SUBG_GLOB_DYNAMIC_TypeDef*) MR_SUBG_GLOB_DYNAMIC_BASE) +#define MR_SUBG_GLOB_STATUS ((MR_SUBG_GLOB_STATUS_TypeDef*) MR_SUBG_GLOB_STATUS_BASE) +#define MR_SUBG_GLOB_MISC ((MR_SUBG_GLOB_MISC_TypeDef*) MR_SUBG_GLOB_MISC_BASE) +#define MR_SUBG_GLOB_RETAINED ((MR_SUBG_GLOB_RETAINED_TypeDef*) MR_SUBG_GLOB_RETAINED_BASE) +#define LPAWUR ((LPAWUR_TypeDef*) LPAWUR_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* ============================================================================================================================*/ +/*===================== SYSCFG =====================*/ +/* ============================================================================================================================*/ + +/* ===================================================== DIE_ID =====================================================*/ +#define SYSCFG_DIE_ID_PRODUCT_Pos (8UL) /*! + + + + + + Release Notes for STM32WL33x CMSIS + + + + + + +
    +
    +
    +

    Release Notes for

    +

    STM32WL3xx CMSIS

    +

    Copyright © 2024 STMicroelectronics
    +

    + +
    +

    Purpose

    +

    This driver provides the CMSIS device for the STM32WL33x products. +This covers

    +
      +
    • STM32WL33x devices
      • +
    +

    This driver is composed of the description of the registers under +“Include” directory.

    +

    Various template files are provided to easily build an application. +They can be adapted to fit applications requirements.

    +
      +
    • Templates/system_stm32wl3x.c contains the initialization code +referred as SystemInit.
      • +
    • Startup files are provided as example for EWARM©.
      • +
    • Linker files are provided as example for EWARM©.
      • +
    +
    +
    +

    Update history

    +
    + + +
    +

    Main Changes

    +
      +
    • Documentation based on jQuery 1.7.1 removed
      • +
    +

    Contents

    +
      +
    • Add PULSETRIM bits definition in CMSIS header files
      • +
    • Renamed some interrupt to improve clarity and consistency
      • +
    • Added FQCY_BAND_ID bits definition for RF_INFO_OUT register
      • +
    +

    Known Limitations

    +
      +
    • CMSIS devices files are delivered “as is” and have not been fully +validated
      • +
    +

    Development Toolchains and +Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
      • +
    +

    Supported Devices and boards

    +
      +
    • STM32WL3xx devices
      • +
    +
    +
    +
    + + +
    +

    Main Changes

    +

    Release

    +
      +
    • Release of CMSIS for STM32WL3xx devices
      • +
    +

    Contents

    +
      +
    • CMSIS devices files for STM32WL3xx
      • +
    +

    Known Limitations

    +
      +
    • CMSIS devices files are delivered “as is” and have not been fully +validated
      • +
    +

    Development Toolchains +and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
      • +
    +

    Supported Devices and +boards

    +
      +
    • STM32WL3xx devices
      • +
    +
    +
    +
    + + +
    +

    Main Changes

    +

    First Release

    +
      +
    • First Official Release of CMSIS for STM32WL33x devices
      • +
    +

    Contents

    +
      +
    • CMSIS devices files for STM32WL33x
      • +
    +

    Known Limitations

    +
      +
    • CMSIS devices files are delivered “as is” and have not been fully +validated
      • +
    +

    Development Toolchains +and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
      • +
    +

    Supported Devices and +boards

    +
      +
    • STM32WL33x devices
      • +
    +
    +
    +
    +
    +
    +
    +
    +

    For complete documentation on STM32 Microcontrollers , visit: +www.st.com/stm32

    +

    This release note uses up to date web standards and, for this +reason, should not be opened with Internet Explorer but preferably with +popular browsers such as Google Chrome, Mozilla Firefox, Opera or +Microsoft Edge.

    +
    +

    Info

    +
    +
    +
    + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld new file mode 100644 index 0000000000..a7f206c3a2 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33x8_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 64KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20003FFF +| RAM (16K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1004FFFF +| | +| FLASH (64K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x4000; /* 16KB */ +_MEMORY_RAM_END_ = 0x20003FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x10000; /* 64KB */ +_MEMORY_FLASH_END_ = 0x1004FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld new file mode 100644 index 0000000000..6f376ad4fb --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xB_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 128KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20007FFF +| RAM (32K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1005FFFF +| | +| FLASH (128K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x8000; /* 32KB */ +_MEMORY_RAM_END_ = 0x20007FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ +_MEMORY_FLASH_END_ = 0x1005FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld new file mode 100644 index 0000000000..e10273958b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL33xC_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 256KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20007FFF +| RAM (32K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1007FFFF +| | +| FLASH (256K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x8000; /* 32KB */ +_MEMORY_RAM_END_ = 0x20007FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x40000; /* 256KB */ +_MEMORY_FLASH_END_ = 0x1007FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld new file mode 100644 index 0000000000..e10273958b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3xx_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 256KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20007FFF +| RAM (32K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1007FFFF +| | +| FLASH (256K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x8000; /* 32KB */ +_MEMORY_RAM_END_ = 0x20007FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x40000; /* 256KB */ +_MEMORY_FLASH_END_ = 0x1007FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s new file mode 100644 index 0000000000..28bf2e6da6 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file : startup_stm32wl3x.s + * @author : GPM WBL Application Team + * @brief : STM32WL3x Ultra Low Power Devices vector + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global __vector_table +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .intvec,"a",%progbits + .type __vector_table, %object + .size __vector_table, .-__vector_table + + +__vector_table: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word FLASH_IRQHandler /* IRQ0: FLASH Controller interrupt */ + .word RCC_IRQHandler /* IRQ1: RCC interrupt */ + .word PVD_IRQHandler /* IRQ2: PVD interrupt */ + .word I2C1_IRQHandler /* IRQ3: I2C1 interrupt */ + .word I2C2_IRQHandler /* IRQ4: I2C2 interrupt */ + .word SPI1_IRQHandler /* IRQ5: SPI1 interrupt */ + .word 0x00000000 /* IRQ6: Reserved */ + .word SPI3_IRQHandler /* IRQ7: SPI3 interrupt */ + .word USART1_IRQHandler /* IRQ8: USART1 interrupt */ + .word LPUART1_IRQHandler /* IRQ9: LPUART1 interrupt */ + .word TIM2_IRQHandler /* IRQ10: TIM2 interrupt */ + .word RTC_IRQHandler /* IRQ11: RTC interrupt */ + .word ADC_IRQHandler /* IRQ12: ADC interrupt */ + .word AES_IRQHandler /* IRQ13: AES interrupt */ + .word 0x00000000 /* IRQ14: Reserved */ + .word GPIOA_IRQHandler /* IRQ15: GPIOA interrupt */ + .word GPIOB_IRQHandler /* IRQ16: GPIOB interrupt */ + .word DMA_IRQHandler /* IRQ17: DMA interrupt */ + .word LPAWUR_IRQHandler /* IRQ18: LPAWUR interrupt */ + .word COMP1_IRQHandler /* IRQ19: COMP1 interrupt */ + .word MRSUBG_BUSY_IRQHandler /* IRQ20: MR SUBG BUSY interrupt */ + .word MRSUBG_IRQHandler /* IRQ21: MR SUBG interrupt */ + .word MRSUBG_TX_RX_SEQUENCE_IRQHandler /* IRQ22: MR SUBG TX RX Sequence interrupt */ + .word MRSUBG_TIMER_CPU_WKUP_IRQHandler /* IRQ23: MR SUBG TIMER CPU Wakeup interrupt */ + .word MRSUBG_WKUP_IRQHandler /* IRQ24: MR SUBG Wakeup interrupt */ + .word DAC_IRQHandler /* IRQ25: DAC interrupt */ + .word TIM16_IRQHandler /* IRQ26: TIM16 interrupt */ + .word LCD_IRQHandler /* IRQ27: LCD interrupt */ + .word LCSC_IRQHandler /* IRQ28: LCSC interrupt */ + .word LCSC_LC_ACTIVITY_IRQHandler /* IRQ29: LCSC LC ACTIVITY interrupt */ + .word 0x00000000 /* IRQ30: Reserved */ + .word 0x00000000 /* IRQ31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak GPIOA_IRQHandler + .thumb_set GPIOA_IRQHandler,Default_Handler + + .weak GPIOB_IRQHandler + .thumb_set GPIOB_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak LPAWUR_IRQHandler + .thumb_set LPAWUR_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak MRSUBG_BUSY_IRQHandler + .thumb_set MRSUBG_BUSY_IRQHandler,Default_Handler + + .weak MRSUBG_IRQHandler + .thumb_set MRSUBG_IRQHandler,Default_Handler + + .weak MRSUBG_TX_RX_SEQUENCE_IRQHandler + .thumb_set MRSUBG_TX_RX_SEQUENCE_IRQHandler,Default_Handler + + .weak MRSUBG_TIMER_CPU_WKUP_IRQHandler + .thumb_set MRSUBG_TIMER_CPU_WKUP_IRQHandler,Default_Handler + + .weak MRSUBG_WKUP_IRQHandler + .thumb_set MRSUBG_WKUP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak LCSC_IRQHandler + .thumb_set LCSC_IRQHandler,Default_Handler + + .weak LCSC_LC_ACTIVITY_IRQHandler + .thumb_set LCSC_LC_ACTIVITY_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c new file mode 100644 index 0000000000..c572cce21c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c @@ -0,0 +1,352 @@ +/** + ****************************************************************************** + * @file system_stm32wl3x.c + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32wl3x.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32wl3x.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32WL3x_system + * @{ + */ + +/** @addtogroup STM32WL3x_System_Private_Includes + * @{ + */ + +#include "stm32wl3x.h" + +/** + * @} + */ + +/** @addtogroup STM32WL3x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WL3x_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (48000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (64000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in SRAM else user remap will be done in FLASH. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x100. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x100. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/*!< HW TRIMMING Defines */ +#define VALIDITY_TAG 0xFCBCECCC /*!< TAG to validate the content of the + trimming area content. */ +#define VALIDITY_LOCATION 0x10001EF8 /*!< ROM address of the the validity trimming values content. */ + +/*!< SMPS Configuration Defines */ +#if !defined(CFG_HW_SMPS) +#define CFG_HW_SMPS SMPS_ON +#endif + +#if !defined(CFG_HW_SMPS_BOM) +#define CFG_HW_SMPS_BOM SMPS_BOM3 /*!< SMPS Inductor 10uH */ +#endif + +#if !defined(CFG_HW_SMPS_LOW_POWER) +#define CFG_HW_SMPS_LOW_POWER SMPS_LOW_POWER_OPEN +#endif + +/** + * @} + */ + +/** @addtogroup STM32WL3x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WL3x_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000U; /* The HSI (64MHz) is used as system clock source after startup from reset, configured at 16 MHz. */ + + /* Crystal frequency */ + uint32_t HSE_xtalFrequency = HSE_VALUE; + + /* The RAM_VR variable is a mirroring in RAM of some registers information. + It is a sort of virtual register in RAM. + */ +#if defined ( __ICCARM__ ) + #pragma location=".ram_vr" + __root __no_init RAM_VR_TypeDef RAM_VR; +#else +#if defined ( __ARMCC_VERSION ) + __attribute__((section(".bss" ".ram_vr"))) +#elif defined ( __GNUC__ ) + __attribute__((section(".ram_vr"))) +#endif + RAM_VR_TypeDef RAM_VR __attribute__((used)); +#endif +/** + * @} + */ + +/** @addtogroup STM32WL3x_System_Private_FunctionPrototypes + * @{ + */ + +void CPUcontextRestore(void); + +/** + * @} + */ + +/** @addtogroup STM32WL3x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + uint32_t mainRegulator, smpsOutVoltage, lsiBw, hsiCalib; + uint8_t i; + + /* If the reset reason is a wakeup from power save restore the context */ + if ((RCC->CSR == 0) && ((PWR->IWUF != 0) || (PWR->WUFA != 0) || (PWR->WUFB != 0))) + { + RAM_VR.WakeupFromSleepFlag = 1; /* A wakeup from power save occurred */ + CPUcontextRestore(); /* Restore the context */ + /* if the context restore worked properly, we should never return here */ + while(1) { + NVIC_SystemReset(); + } + } + + /* Configure the Vector Table location */ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#else + SCB->VTOR = (uint32_t) (__vector_table); +#endif /* USER_VECT_TAB_ADDRESS */ + + /* Store in RAM the AppBase information */ + RAM_VR.AppBase = (uint32_t) SCB->VTOR; + + /* Enable all the RAM banks in retention during power save */ + SET_BIT(PWR->CR2, PWR_CR2_RAMRET1); + + /* Disable the GPIO retention in power save configuration */ + CLEAR_BIT(PWR->CR2, PWR_CR2_GPIORET); + + /* SMPS setup */ + if ((CFG_HW_SMPS == SMPS_ON) || (CFG_HW_SMPS == SMPS_STATIC_BOF) || (CFG_HW_SMPS == SMPS_DYNAMIC_BOF)) + { + while(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) != PWR_SR2_SMPSRDY); // Wait until SMPS is ready + MODIFY_REG(PWR->CR5, PWR_CR5_SMPSBOMSEL, (CFG_HW_SMPS_BOM<CR5, PWR_CR5_NOSMPS, (CFG_HW_SMPS<CR5, PWR_CR5_NOSMPS_BOF); + CLEAR_BIT(PWR->CR5, PWR_CR5_SMPS_BOF_DYN); + SET_BIT(PWR->CR5, PWR_CR5_SMPS_BOF_STATIC); + } + if (CFG_HW_SMPS == SMPS_DYNAMIC_BOF) + { + /* The SMPS output voltage level and SMPS BOF tuning are set to 1.4V by default */ + SET_BIT(PWR->CR5, PWR_CR5_NOSMPS_BOF); + CLEAR_BIT(PWR->CR5, PWR_CR5_SMPS_BOF_STATIC); + SET_BIT(PWR->CR5, PWR_CR5_SMPS_BOF_DYN); + } + MODIFY_REG(PWR->CR5, PWR_CR5_SMPSLPOPEN, (CFG_HW_SMPS_LOW_POWER<CSSWCR, RCC_CSSWCR_HSITRIMSW, hsiCalib << RCC_CSSWCR_HSITRIMSW_Pos); + SET_BIT(RCC->CSSWCR, RCC_CSSWCR_HSISWTRIMEN); + + /* Low speed internal RC trimming value set by software */ + MODIFY_REG(RCC->CSSWCR, RCC_CSSWCR_LSISWBW, lsiBw << RCC_CSSWCR_LSISWBW_Pos); + SET_BIT(RCC->CSSWCR, RCC_CSSWCR_LSISWTRIMEN); + + /* Set Main Regulator voltage Trimming value */ + MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_TRIM_MR, ((mainRegulator << PWR_ENGTRIM_TRIM_MR_Pos) & PWR_ENGTRIM_TRIM_MR)); + SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_TRIMMREN); + + /* Set SMPS output voltage Trimming value */ + MODIFY_REG(PWR->ENGTRIM, PWR_ENGTRIM_SMPS_TRIM, ((smpsOutVoltage << PWR_ENGTRIM_SMPS_TRIM_Pos) & PWR_ENGTRIM_SMPS_TRIM)); + SET_BIT(PWR->ENGTRIM, PWR_ENGTRIM_SMPSTRIMEN); + } + + /* Set all the interrupt with low priprity */ + for (i=0; i<32; i++) + { + NVIC_SetPriority((IRQn_Type)i, IRQ_LOW_PRIORITY); + } + + /* Enable all the irqs */ + __enable_irq(); +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t directHSE_enabled; + uint8_t divPrescaler; + + /* Get SYSCLK source HSE or HSI+PLL64MHz */ + directHSE_enabled = (RCC->CFGR & RCC_CFGR_HSESEL) >> RCC_CFGR_HSESEL_Pos; + + /* Get the clock divider */ + divPrescaler = (RCC->CFGR & RCC_CFGR_CLKSYSDIV_STATUS) >> RCC_CFGR_CLKSYSDIV_STATUS_Pos; + + if (directHSE_enabled) + { + switch(divPrescaler) + { + case 0: + SystemCoreClock = HSE_VALUE; + break; + case 1: + SystemCoreClock = HSE_VALUE/2; + break; + default: + SystemCoreClock = HSE_VALUE/(3*(1<<(divPrescaler-2))); + break; + } + } + else + { + SystemCoreClock = HSI_VALUE >> divPrescaler; + } +} + +/** + * @brief Restores the saved CPU state before to enter in power save + * by popping it from the stack + * @param None + * @retval None + */ +__WEAK void CPUcontextRestore(void) +{ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/Add button.svg b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/Add button.svg new file mode 100644 index 0000000000..c211545dad --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/Add button.svg @@ -0,0 +1,2 @@ + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/Update.svg b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/Update.svg new file mode 100644 index 0000000000..f88381f1e6 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/Update.svg @@ -0,0 +1,2 @@ + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/favicon.png b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/favicon.png new file mode 100644 index 0000000000..06713eec49 Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/favicon.png differ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/mini-st_2020.css b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/mini-st_2020.css new file mode 100644 index 0000000000..db8b406aa4 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/mini-st_2020.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/st_logo_2020.png b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/st_logo_2020.png new file mode 100644 index 0000000000..d6cebb5ac7 Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32WL3x/_htmresc/st_logo_2020.png differ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h index 5e2d09d4b8..6df84f0ff2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h @@ -80,7 +80,7 @@ * @brief CMSIS Device version number */ #define __STM32WLxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32WLxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WLxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WLxx_CMSIS_DEVICE_VERSION ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/LICENSE.md b/system/Drivers/CMSIS/Device/ST/STM32WLxx/LICENSE.md new file mode 100644 index 0000000000..261eeb9e9f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WLxx/LICENSE.md @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/README.md b/system/Drivers/CMSIS/Device/ST/STM32WLxx/README.md index 5106f6ab9f..3624ca6420 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WLxx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32WLxx/README.md @@ -1,19 +1,21 @@ # STM32CubeWL CMSIS Device MCU Component -## Overview +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis-device-wl.svg?color=brightgreen) -**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. +## Overview of the STM32Cube MCU offer on GitHub -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... - * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series +**STM32Cube** is an original initiative by STMicroelectronics to **simplify** prototyping and development by **reducing** effort, time, and cost. It supports the entire ARM™ Cortex-based STM32 microcontroller portfolio and provides a **comprehensive** software solution including: + * The CMSIS Core and Device interfaces enabling access to processor core features and device-specific peripherals of STM32 microcontrollers. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers enabling access to peripherals on the STM32 development boards, external to the microcontroller itself. + * A consistent set of middleware libraries offering standardized, high-level functionalities — such as USB, TCP/IP, file systems, and graphics. + * A full set of software projects (basic examples, applications, and demonstrations) that showcase specific functionalities or use cases, and provided with support for multiple IDEs. -Two models of publication are proposed for the STM32Cube embedded software : - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. +The **STM32Cube embedded software** is available in two flavors: + * The **MCU Firmware** _monolithic_ offer, where **all** software components (Drivers, Middleware, Projects, Utilities) are included in a **single** repository for each STM32 series. + * The **MCU Software Components** _modular_ offer, where **each** software component (mainly Drivers and Middleware) is provided in a **dedicated** repository, allowing users to **select** only the components they need. + +The complete list of repositories is available [here](https://github.com/STMicroelectronics/STM32Cube_MCU_Overall_Offer/blob/master/README.md#content). ## Description @@ -21,15 +23,12 @@ This **cmsis_device_wl** MCU component repo is one element of the STM32CubeWL MC ## Release note -Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_wl/blob/master/Release_Notes.html). +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis-device-wl/blob/main/Release_Notes.html). ## Compatibility information It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWL/blob/main/Release_Notes.html) release note. -The full **STM32CubeWL** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWL). - -## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_wl/issues/new). +## Feedback and contributions -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Release_Notes.html index 6818b339a0..cd7eeeee36 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Release_Notes.html @@ -5,16 +5,24 @@ Release Notes for STM32WLxx CMSIS - - @@ -25,10 +33,12 @@

    Release Notes for

    STM32WLxx CMSIS

    Copyright © 2020 STMicroelectronics

    - +

    Purpose

    -

    This driver provides the CMSIS device for the stm32WLxx products. This covers

    +

    This driver provides the CMSIS device for the stm32WLxx products. +This covers

    • STM32WL55xx devices
    • STM32WL54xx devices
      • @@ -36,24 +46,35 @@

      Purpose

    • STM32WLE4xx devices
    • STM32WL5Mxx devices
    -

    This driver is composed of the descriptions of the registers under “Include” directory.

    -

    Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

    +

    This driver is composed of the descriptions of the registers under +“Include” directory.

    +

    Various template file are provided to easily build an application. +They can be adapted to fit applications requirements.

      -
    • Templates/system_stm32WLxx.c contains the initialization code referred as SystemInit.
      • -
    • Startup files are provided as example for IAR©, KEIL© and STM32CubeIDE©.
      • -
    • Linker files are provided as example for IAR©, KEIL© and STM32CubeIDE©.
      • +
    • Templates/system_stm32WLxx.c contains the initialization code +referred as SystemInit.
      • +
    • Startup files are provided as example for IAR©, KEIL© and +STM32CubeIDE©.
      • +
    • Linker files are provided as example for IAR©, KEIL© and +STM32CubeIDE©.
-
-

Update History

+
+

Update History

- + +

Main Changes

    -
  • Add new device STM32WL5Mxx
    • -
  • Rename ADC_TRx to ADC_AWDxTR to match with Reference Manual
    • -
  • Fix inconsistent IRQn_Type enumeration for supervisor call exception with alias for compatibility
    • +
  • Update STM32CubeIDE projects to fix the location of .size directive +in startup code to allow proper size information of vector table
    • +
  • Change addresses of ROM symbols in sram.icf +template files to code region alias in order to increase performance +while running code from SRAM
    • +
  • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from +the IDE, makefile, or command line.

Known Limitations

None

@@ -64,11 +85,16 @@

Notes

- + +

Main Changes

    -
  • All source files and templates: update disclaimer to add reference to the new license agreement
    • +
  • Add new device STM32WL5Mxx
    • +
  • Rename ADC_TRx to ADC_AWDxTR to match with Reference Manual
    • +
  • Fix inconsistent IRQn_Type enumeration for supervisor call exception +with alias for compatibility

Known Limitations

None

@@ -79,17 +105,14 @@

Notes

- + +

Main Changes

    -
  • Add atomic register access services: -
      -
    • 32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), ATOMIC_MODIFY_REG()
      • -
    • 16-bit register access: ATOMIC_SETH_BIT(), ATOMIC_CLEARH_BIT(), ATOMIC_MODIFYH_BIT()
      • -
    • -
  • Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)
    • -
  • Add reference to user manual for customization of CubeIDE linker files
    • +
  • All source files and templates: update disclaimer to add reference +to the new license agreement

Known Limitations

None

@@ -100,12 +123,24 @@

Notes

- + +

Main Changes

-

First Official Release

-

Contents

-

First official release of CMSIS drivers for STM32WLxx lines

+
    +
  • Add atomic register access services: +
      +
    • 32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), +ATOMIC_MODIFY_REG()
      • +
    • 16-bit register access: ATOMIC_SETH_BIT(), ATOMIC_CLEARH_BIT(), +ATOMIC_MODIFYH_BIT()
      • +
    • +
  • Add define LSI_STARTUP_TIME used in default IWDG timeout calculation +(HAL_IWDG_DEFAULT_TIMEOUT)
    • +
  • Add reference to user manual for customization of CubeIDE linker +files
    • +

Known Limitations

None

Dependencies

@@ -114,13 +149,34 @@

Notes

None

+
+ + +
+

Main Changes

+

First Official Release

+

Contents

+

First official release of CMSIS drivers for STM32WLxx lines

+

Known Limitations

+

None

+

Dependencies

+

None

+

Notes

+

None

+
+