[Summary]Hello,
I am using the HDL Coder Workflow Advisor to perform FPGA-in-the-Loop (FIL) verification. The workflow completes without errors and the FIL block is generated, but I'm having an issue where its output does not match the output of the original Simulink model (the expected value).
This problem is reproducible even with a very simple adder model. The attached Scope image shows a comparison of the outputs from that test. As you can see, there is a clear discrepancy between the expected value (dut_ref) and the FIL block's output.
Attached Image:
[Environment]
- MATLAB Version: R2025a
- HDL Coder Version: R2025a
- Target Tool: Xilinx Vivado 2024.2
- Target Device: Arty Z7-20
[Problem Details and Investigation]To investigate this issue, I generated a FIL block from a simple two-input adder model. The Synthesis & Implementation process in Vivado completes without errors, and the bitstream file is generated successfully. I have also confirmed that the generated wrapper HDL file correctly instantiates my adder design (the DUT).
However, when I run the FIL block in Simulink, the output is incorrect as shown in the image above. It appears that for some reason, the data transfer between Simulink and the physical FPGA is not occurring correctly.
[What I've Tried]
- I have lowered the target frequency to 25 Hz, and the problem still occurs, so I believe it is unlikely to be a timing issue.
- The same issue occurs after deleting the fil_prj folder and performing a clean rebuild.
[Questions]
- In a situation like this, where synthesis and implementation complete without error, yet the FIL block's behavior differs from the expected value, what are the other possible causes?
- Are there any other points to check or effective approaches to debug this problem?
- Is this a known issue with specific tool versions?
Thank you for your time and assistance.
