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1

answer

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Why do I receive the message "No matching files were found" in HDL Workflow Advisor Step 4.2 "Build FPGA Bitstream"?

Asked by MathWorks Support Team on 21 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
50 views

Troubleshooting connection issues with Xilinx Zynq platform

Asked by MathWorks Support Team on 3 Jul 2018

Latest activity Edited by MathWorks Support Team on 4 Mar 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

PDF Documentation for "Deep Learning HDL Toolbox Support Package for Intel / Xilinx FPGA and SoC Devices"

Asked by MathWorks Support Team on 14 Oct 2020

Latest activity Edited by MathWorks Support Team on 24 Dec 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Find Documentation, Examples and more on HDL Coder Supported Hardware in Help Center

2

answers

0 votes
21 views

How can I use a custom board with the Zynq workflow provided by MATLAB/Simulink?

Asked by MathWorks Support Team on 17 Jul 2021

Latest activity Edited by MathWorks Support Team on 7 Jun 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

When I right click on a Xilinx System Generator block in Simulink, why do I get errors in MATLAB?

Asked by MathWorks Support Team on 1 Feb 2019

Latest activity Edited by MathWorks Support Team on 15 Sep 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Why do I encounter an error message when I attempt to generate code for a Xilinx System Generator Subsystem?

Asked by MathWorks Support Team on 13 Dec 2016

Latest activity Answered by MathWorks Support Team on 9 Jan 2017

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Find Code on HDL Coder Supported Hardware in File Exchange

1

answer

0 votes
2 views

Why do I get an error about a missing "thirdpartytools_win64.xml" file when I try to build my model for Xilinx Zynq platform?

Asked by MathWorks Support Team on 21 Jul 2016

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why am I getting a "SD card is read-only" error during hardware setup for HDL Verifier Support Package for Xilinx FPGA Boards?

Asked by MathWorks Support Team on 10 Jan 2024

Latest activity Answered by MathWorks Support Team on 19 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

1 vote
1 view

Is it possible to get the source code for the Linux kernel that MathWorks uses to create the images for the Zynq support packages?

Asked by MathWorks Support Team on 8 Feb 2021

Latest activity Edited by MathWorks Support Team on 21 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
10 views

How do you generate HDL code for the Artix-7 family of boards? What is the recommended workflow for this?

Asked by MathWorks Support Team on 7 Jun 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Do I have to install a third-party synthesis tool to use HDL Coder?

Asked by MathWorks Support Team on 30 Mar 2021

Latest activity Edited by MathWorks Support Team on 1 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
18 views

Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

Asked by MathWorks Support Team on 17 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

How do I reduce resource utilization for an AXI4-Stream interface generated using HDL Coder?

Asked by MathWorks Support Team on 3 May 2021

Latest activity Answered by MathWorks Support Team on 3 May 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
8 views

Zynq workflow: Software interface model build fails due to error regarding missing "iio.h" file

Asked by MathWorks Support Team on 19 Jan 2022

Latest activity Answered by MathWorks Support Team on 20 Jan 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
12 views

How can I use HDL Coder with an unsupported or custom FPGA board?

Asked by MathWorks Support Team on 28 Jan 2022

Latest activity Edited by MathWorks Support Team on 17 Jul 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
29 views

Why do I get the Vivado error message "Specified part could not be found" during IP Core Generation with HDL Workflow Advisor or SoC Builder?

Asked by MathWorks Support Team on 26 Jul 2023

Latest activity Edited by MathWorks Support Team on 12 Feb 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why does "Monitor and Tune" fail even though I built and compiled my code successfully with a precompiled shared library using MATLAB Coder?

Asked by MathWorks Support Team on 2 Nov 2023

Latest activity Answered by MathWorks Support Team on 2 Nov 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
10 views

Do the "ADC/DAC Interface" reference designs support Vivado 2022.1 or later?

Asked by MathWorks Support Team on 24 May 2023

Latest activity Edited by MathWorks Support Team on 13 May 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

How can I set properties such as Verilog Include Directories in the FILWIZARD of HDL Verifier 4.1 (R2012b)?

Asked by MathWorks Support Team on 11 Apr 2013

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Can I define customized Bus Data Types as input data types to HDL Coder DUT?

Asked by MathWorks Support Team on 31 Jan 2019

Latest activity Edited by MathWorks Support Team on 18 Aug 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
5 views

When using the HDL Workflow Advisor, why do I get errors in Task 1.2 that mention "Dot indexing is not support for variables of this type"?

Asked by MathWorks Support Team on 18 Sep 2019

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Using HDL Coder, how can I do partial streaming of a MATLAB loop?

Asked by MathWorks Support Team on 9 Oct 2018

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

How can I modify the HDL Compilation commands when doing cosimulation using the Cosimulation Wizard?

Asked by MathWorks Support Team on 23 Jul 2018

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

Why does "hdldispmdlparams" return model parameters when "gcb" is passed in?

Asked by MathWorks Support Team on 13 Jan 2021

Latest activity Answered by MathWorks Support Team on 13 Jan 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Error while installing the "Embedded Coder Support Package for Xilinx Zynq Platform"

Asked by MathWorks Support Team on 5 Aug 2020

Latest activity Edited by MathWorks Support Team on 11 Dec 2020

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

How do I display multiple flagged objects in separate lines for "ModelAdvisor.ResultDetail"?

Asked by MathWorks Support Team on 2 Jan 2024

Latest activity Answered by MathWorks Support Team on 5 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices Generate an IP Core and Bitstream Custom Board and Reference Design

1

answer

0 votes
4 views

Is the Xilinx Platform Cable USB II supported for FIL simulation?

Asked by MathWorks Support Team on 9 May 2019

Latest activity Edited by MathWorks Support Team on 10 Nov 2025 at 11:50

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
20 views

Why am I getting the error "The board files for the target platform were not found" in 'Create Project' step in HDL Workflow Advisor?

Asked by MathWorks Support Team on 9 Sep 2025

Latest activity Edited by MathWorks Support Team on 6 Nov 2025 at 17:17

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
1 view

How can I create an HDL Coder IP core that accesses multiple external memory locations with External DDR4 Memory Access?

Asked by MathWorks Support Team on 6 Aug 2025

Latest activity Answered by MathWorks Support Team on 27 Aug 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
1 view

How can I connect multiple AXI DMAs to a reference design in HDL Coder?

Asked by MathWorks Support Team on 30 Jun 2025

Latest activity Answered by MathWorks Support Team on 24 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
0 views

How to programmatically add an FPGA board from a FPGA board definition XML in MATLAB R2023b?

Asked by MathWorks Support Team on 15 Apr 2025

Latest activity Answered by MathWorks Support Team on 15 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
0 views

Why am I getting a 'the path "Zynq\firmware\R22_1_0\sysroot_zynqmp' does not exist" error when using generating code for Xilinx Zynq platform?

Asked by MathWorks Support Team on 13 Jul 2022

Latest activity Edited by MathWorks Support Team on 24 Dec 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

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