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Which versions of Vivado are supported with which release of HDL Coder?

Asked by MathWorks Support Team on 16 Apr 2020

Latest activity Edited by MathWorks Support Team on 29 Sep 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

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How can I connect multiple AXI DMAs to a reference design in HDL Coder?

Asked by MathWorks Support Team on 30 Jun 2025

Latest activity Answered by MathWorks Support Team on 24 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

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Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

Asked by MathWorks Support Team on 17 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

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How do I add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder?

Asked by MathWorks Support Team on 4 Apr 2019

Latest activity Edited by MathWorks Support Team on 27 Jun 2025

Accepted Answer by MathWorks Support Team

Code Generation Embedded Coder Deployment, Integration, and Supported Hardware Embedded Coder Supported Hardware Intel SoC Devices

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Why do I receive the error "unable to allocate delays to compensate for the N delays introduced by BLOCK in native floating point mode"?

Asked by MathWorks Support Team on 4 Feb 2019

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

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In R2018a, how can I force HDL Coder to generate HDL code for a lookup table to use RAM or Block RAM?

Asked by MathWorks Support Team on 16 Aug 2018

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

2

answers

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How do I generate HDL code from a masked subsystem that is not at the model's root level in Simulink?

Asked by MathWorks Support Team on 20 Jun 2017

Latest activity Edited by MathWorks Support Team on 12 Apr 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

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1

Which versions of Vivado are supported with which release of HDL Coder?

1

How can I connect multiple AXI DMAs to a reference design in HDL Coder?

1

Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

2

How do I add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder?

1

Why do I receive the error "unable to allocate delays to compensate for the N delays introduced by BLOCK in native floating point mode"?

1

In R2018a, how can I force HDL Coder to generate HDL code for a lookup table to use RAM or Block RAM?

2

How do I generate HDL code from a masked subsystem that is not at the model's root level in Simulink?