Using an if else condition in a generate block in Verilog

Question

I have a code where I am using recursion,

module mult(a,b,c)
  generate
    always @(*) begin
     /* a few calculations */
     if(x < 10)
       flag = 1;
     else
       flag = 0; 
    end
     if( flag == 1)
        mult(x,y,z);
     else
        z = x*y;
  endgenerate
endmodule

However, this code returns an error saying that flag is not a constant. I understand that one cannot use an if-else outside the always block, by using registers or wires or integers. However, is there any other way I can implement the code?

Recursion seems to work only in a generate block but outside the always block.

Brian Magnuson · Accepted Answer · 2012-12-12 02:22:51Z

1

Conditionals in generate blocks need to be constant at elaboration time. Typically they either `defines or parameters of the module.

You don't declare 'x' at all in your example... In fact there are numerous errors that would prevent this from compiling. Enough that it's hard to figure our your intent. Can you provide a bit of detail on this?

answered Dec 12, 2012 at 2:22

Brian Magnuson

1,4971 gold badge9 silver badges15 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

Using an if else condition in a generate block in Verilog

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related