cannot use an input for if statement in Verilog

It's my understanding that the first statement in a verilog always block must be the if(reset) term if you're using an asynchronous reset.

So the flop construct should always look like this:

always @ (posedge clk or negedge rst_n) begin
   if(~rst_n) begin
       ...reset statements...
   end else begin
       ...all other statements...
   end
end

So for your case you should move the if(clockHandler==0) block inside the else statement, because it is not relevant to the reset execution. Even better would be to move it into a separate combinational always block, since mixing blocking and nonblocking statements inside an always block is generally not a good idea unless you really know what you're doing. I think it is fine in your case though.

To add to Tim's answer - the original code (around line 17, anyway) is valid Verilog.

What it's saying is "whenever there's a rising edge on clk or a falling edge on rst_n, check clockHandler and do something" (by the way, get rid of the begin/ends; they're redundant and verbose). The problem comes when you want to implement this in real hardware, so the error message is presumably from a synthesiser, which needs more than valid Verilog. The synth suspects that it has to build a synchronous element of some sort, but it can't (or won't, to be precise) handle the case where clockHandler is examined on an edge of both clk and rst_n. Follow the rules for synthesis templates, and you won't get this problem.

is this a compilation error or synthesis error? i used the same code to see if it compiles fine, and i din get errors.. Also, it is recommended to use "<=" inside synchronous blocks rather than "="

You're using the same flop construct for two different things. Linearly in code this causes a slipping of states. I always place everything within one construct if the states rely on that clock or that reset, otherwise you require extra steps to make sure more than one signal isn't trying to change your state.

You also don't need the begin/end when it comes to the flop construct, Verilog knows how to handle that for you. I believe Verilog is okay with it though, but I generally don't do that. You also don't have to use it when using a single statement within a block.

So your first module would look like this (if I missed a block somewhere just let me know):

clock_divider.v module (edited)

module clock_divider (clockHandler, clk, rst_n, clk_o);

parameter DIV_CONST = 10000000 ;  // 1 second
parameter DIV_CONST_faster = 10000000 / 5;
input clockHandler;
input clk;
input rst_n;

output reg clk_o;

reg [31:0] div;
reg en;
integer div_helper = 0;

always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        div <= 0;
        en <= 0;
        clk_o <= 1'b0;
    end
    else if(en)
    begin
        clk_o <= ~ clk_o;

        if(clockHandler == 0)
        begin 
            div_helper = DIV_CONST;
        end
        else
        begin 
            div_helper = DIV_CONST_faster;
        end
        else
        begin
            if (div == div_helper)
            begin 
                div <= 0;
                en <= 1;
            end
        end
        else
        begin 
            div <= div + 1;
            en <= 0;
        end
    end
end
end module

If that clk_o isn't meant to be handled at the same time those other operations take place, then you can separate everything else with a general 'else' statement. Just be sure to nest that second construct as an if-statement to check your state.

And also remember to add always @ (posedge clk or negedge rst_n) to your main.v module as Tim mentioned.