Verilog Conditional Expression

Question

please can anyone help me writing the two conditional statements such that both should give same output...eg:

If I write the in the way mentioned below it is giving the output but with large amount of delay

if(count==3'd2 || i<=16'd8192) begin
  count = 3'd1;
  AL1   = x[i]+x[i+1];
  DL1   = x[i]-x[i+1];
  i     = i+2;
end
else begin
  count = count+1'd1;
  i     = 16'd0;
end

I am getting error if write code in this way...

if (i<=16'd8192) begin
   if (count==3'd2) begin
     count = 3'd1;
     AL1   = x[i]+x[i+1];
     DL1   = x[i]-x[i+1];
     i     = i+2;
   end
   else begin
     count = count+1'd1;
   end
 else begin
   i       = 16'd0;
 end

Please help me out of this

Morgan · Accepted Answer · 2014-01-09 17:57:52Z

1

Was the problem the code was not functionally the same or was it a syntax error?

Both code examples had a trailing end which I have removed when formatting the code in the question.

Verilogs begin end syntax for an if statement is:

if ( condition a ) begin
  // a true
end
else begin
  // a false
end

With a secondary embedded conditional it would be:

if ( condition a ) begin
  if ( condition b ) begin
    // a & b true
  end
  else begin
    // a true b false
  end 
end
else begin
  // a false
end

If this was the issue adopting a stricter indentation style when coding will help spot these errors.

answered Jan 9, 2014 at 17:57

Morgan

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2 Comments

user3178637 Over a year ago

I tried to run the code using second method...but i faced some errors initially ...now i got the output..Thank you Morgan..

Morgan Over a year ago

@user3178637 Excellent.

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