verilog : Instantiation of modules in generate block with variable inputs

Question

I have just started with verilog and trying to implement a small block where I want to call a module inside the generate block but with variable parameters, like:

module abc(a,b,c,d)
input a,b;
output c,d;

generate
if(a=1) begin
xyz xyz1(a,b,c,d);
end 
if(a=0) begin
efj xyz1(a,b,c,d);
endgenerate

endmodule

The values of a and b are changing at every clock cycle. I know we can only use constant values in generate block but how can I handle this? Is there any way out?

You do not call verilog modules you instantiate. They represent physical blocks of hardware. You can not create and dispose of them on the fly. — Morgan
– Morgan, Commented Mar 15, 2014 at 8:18

Ari · Accepted Answer · 2014-03-15 00:39:04Z

1

Looks like you need both modules simultaneously, so instantiate them without generate, but connect their outputs to the output of abc based on a's value:

module abc(a,b,c,d);
  input a,b;
  output reg c,d;
  wire c1, d1, c2, d2;
  xyz xyz1(a,b,c1,d1);
  efj xyz2(a,b,c2,d2);

  always @(*)
   if (a==1) begin 
     c=c1; d=d1;
   end
   else begin
     c=c2; d=d2;
   end

endmodule

Also, you should use == operator, rather than = operator in the if statements.

answered Mar 15, 2014 at 0:39

Ari

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6 Comments

Ari Over a year ago

@user3380728: What you want is usually done using a multiplexer. Consider an ALU for example, usually, you have several modules each implementing an operation. The output of each module goes into a mux, and the opcode is used as the select of the mux. Here is an example: cs.nyu.edu/~gottlieb/courses/2011-12-fall/arch/diagrams/…

Ari Over a year ago

The always block in my answer behaves like a mux. If you really want only one sub-module to see the changes of input operands and block the others, you can use a technique called "Operand isolation", but I doubt that is what you want to do here. en.wikipedia.org/wiki/Operand_isolation

user3380728 Over a year ago

Thanks Ari..it is working fine but I think its a very costly operation of calling all the modules at the start. Can something be done about it?

Qiu Over a year ago

@user3380728: in HDL all modules you're calling are generated at the start.

Ari Over a year ago

Unlike software, you can't create hardware on the fly unless you do something fancy like reprogramming your fpga based on some input value.

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