vhdl assign specific bit of std_logic_vector with index failed

Question

I tried to do this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_8to1 is
    Port ( Y : in  STD_LOGIC_VECTOR (0 to 7);
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           F : out  STD_LOGIC);
end mux_8to1;

architecture Behavioral of mux_8to1 is
begin
  run: for i in 0 to 7 generate
    F <= Y(i) when S = i else
         '0';
  end generate run;

end Behavioral;

but the Xilinx report an error to me

ERROR:Xst:528 - Multi-source in Unit <mux_8to1> on signal <F>

Is that the index can't be used in the input or somewhere?

Morten Zilmer · Accepted Answer · 2014-08-01 16:50:00Z

3

The synthesis tool will unroll the generate loop, resulting in:

F <= Y(0) when S = 0 else '0';
F <= Y(1) when S = 1 else '0';
...
F <= Y(7) when S = 7 else '0';

Whereby you can see that F has multiple drivers, which is exactly what the Xilinx synthesis complains about.

A way to make the mux using the non-standard VHDL package std_logic_unsigned, is to replace the run: for ... with:

F <= Y(conv_integer(S));

An just to show how to make with loop, the code is:

process (Y, S) is
begin
  F <= 'X';  -- Default to avoid latch if no resulting driver in loop
  for i in 0 to 7 loop
    if S = i then
      F <= Y(i);
    end if;
  end loop;
end process;

As per inspiration from Jim Lewis comment, the code using standard VHDL-2002 package numeric_std with:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Is in short form:

F <= Y(to_integer(unsigned(S)));

And using loop:

process (Y, S) is
begin
  F <= 'X';  -- Default to avoid latch if no resulting driver in loop
  for i in 0 to 7 loop
    if unsigned(S) = i then
      F <= Y(i);
    end if;
  end loop;
end process;

edited Aug 1, 2014 at 16:50

answered Aug 1, 2014 at 9:24

Morten Zilmer

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1 Comment

Jim Lewis Over a year ago

Using the standard, numeric_std, to do Morten's shortcut: F <= Y(std_logic_vector(to_integer(S))) ; or with the VHDL-2008 package numeric_std_unsigned (may not yet be supported in your synthesis tool), you can do: F <= Y(to_integer(S)) ;

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