Generate Statement in verilog for multiple Blocks

Question

In the code you can see that, I want to instantiate LSFR_counter for 8 times using generate statement. It simulated well, but I want to synthesize for FPGA.

I have problems which are:

1) I found an error when synthesized it.

Line 31: Signal Reg[4] in unit Main is connected to following multiple drivers:

2) Can I use random parameter for #(.n(random))?

module Main( output Reg , input clk , input reset );     

 parameter N =5 ;
 wire  [N-1:0] Reg ; 
 generate    
   genvar i =0 ;
   for (i ; i<8 ; i=i+1 )
   begin 
   LSFR_counter   #(.n(5)) F1  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );  
   end 
 endgenerate 
endmodule

and

    module LSFR_counter  #(parameter n=6)( output Reg, input clk, input reset);
    //parameter n=6; // Change more than n to change LFSR length.

    reg [n:1]Reg; //All procedure outputs must be registered

    always @(posedge clk or posedge reset)
        if
        (reset) Reg <=1;
        else
        Reg <= {Reg[n-1:2], Reg[n]^Reg[1], Reg[n]};
    endmodule

Morgan · Accepted Answer · 2015-02-20 18:01:34Z

2

Multiple divers means that you have multiple modules trying to set the value of Reg. As a side note I really would advise to use some thing else other than Reg as a signal name, not least because at the top level it is a wire.

Thinking about your generate around the LFSR it would unroll to something like:

LSFR_counter   #(.n(5)) F1_1  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );
LSFR_counter   #(.n(5)) F1_2  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );
LSFR_counter   #(.n(5)) F1_3  ( .Reg (Reg )  , .clk (clk ), .reset(reset) );

clk and reset are inputs and they can drive multiple modules, but reg is an output which all of them are trying to drive.

In simulation you may not see an issue as you have multiple modules all driving the exact same value.

You likely wanted some thing along the lines of:

wire  [N-1:0] Reg [0:7]; //<-- memory
genvar i =0 ;   
generate    
  for (i ; i<8 ; i=i+1 ) begin 
    LSFR_counter #(
     .n(5)
    ) F1  ( 
     .Reg  (Reg[i]  ), //<-- write to part of memory
     .clk  (clk  ),
     .reset(reset) 
    );  
  end 
endgenerate

edited Feb 20, 2015 at 18:01

answered Feb 20, 2015 at 12:10

Morgan

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4 Comments

Misal313 Over a year ago

Thank you Sir @ Morgan... you gave me the answer of my first question. can you please tell me that here i used #(.n(5)) 5 as parameter . instead of constant 5 i want to put eight different number as for loop wil repat eight times. every loop must have its own different parameter ..

Morgan Over a year ago

@fame313 Do you know why you want different lengths? It might help me guide the answer. Also your LFSRs are outputting the full width of the state. Which we know to be bad as it is highly correlated. This currently gives you the problem that they will all be different lengths so will not fill a memory or array. IF you could output only 2 bits from each LFSR the problem is much easier.

Misal313 Over a year ago

ok .. is it possible from LSFR that after completing cycle, it can generate different random sequence ? actually i want different sequence state for random of 2^n . but here LSFR gives the same random sequence for every cycle.

Morgan Over a year ago

The polynomial used defines the sequence, in your previous questions a LFSR with the POLYNOMIAL as a parameter is used. you jsut need to drive that from a register and detect when your back at the start of the sequence and change the polynomial. but why do you not just use a LFSR of greater length?

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