VHDL how to use a std_logic_vector as index for an array

Question

I want to use std_logic_vector as index for an array, for example:

Data: in std_logic_vector(7 downto 0);
signal counter : std_logic_vector(3 downto 0);

output <= Data(counter);

Since VHDL syntax check tells me that I should use an integer with Data as index, I want to ask if it's possible to use an std_logic_vector as index.

In case not, if I use a counter like this:

signal counter : integer range 0 to 7 := 7;

Synthesizer will create a 8 bit counter(because 7 is maximum value) or it will create a 32bit counter? I ask this question becouse if I assign a value of 8 to counter vhdl syntax check doesn't tell me that is an error.

Synthesizer don't enforce VHDL standard (unlike a good simulator like ModelSim). Assigning 8 to a range 0 to 7 is illegal by VHDL standard. A synthesizer might accept it (and probably assign 0), but you really shouldn't rely on that. — Jonathan Drolet
– Jonathan Drolet, Commented Apr 18, 2015 at 14:24

Timmy Brolin · Accepted Answer · 2015-04-18 14:04:50Z

6

To use std_logic_vector, you have to convert it:

Data: in std_logic_vector(7 downto 0);
signal counter : std_logic_vector(3 downto 0);

output <= Data(to_integer(unsigned(counter)));

Regarding your second question, this will be a 3 bit counter:

signal counter : integer range 0 to 7 := 7;

Physically, integer and std_logic_vector makes no difference. It will result in exactly the same hardware after synthesis. Use the data type that makes most sense in your code.

answered Apr 18, 2015 at 14:04

Timmy Brolin

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