Verilog Parameterized macro usage

Question

I am trying to use parameterized macros in Verilog to dynamically change the master module of instances through macro names as tried below.

`define AND_CELL(tech) ``tech``_2oi1_1x 

`define TECH_1 tech1
`define TECH_2 tech2

module top(in1, in2, in3, in4, out_x);
  input in1, in2, in3, in4;
  output out_x;
  wire t1_c, t2_c;

  `AND_CELL(`TECH_1) u1(.a(in1), .b(in2), .x(t1_c));
  `AND_CELL(`TECH_2) u2(.a(in3), .b(in4), .x(t2_c));

  assign out_x = t1_c | t2_c ;
endmodule

module tech1_2oi1_1x(a, b, x);
  input a, b;
  output x;
  assign x = a & b;
endmodule

module tech2_2oi1_1x(a, b, x);
  input a, b;
  output x;
  assign x = a & b;
endmodule

The intent here to have the top module to have two different AND gates based on the TECH_1 and TECH_2 macro values.

My attempt gives syntax error while compiling the RTL, as below:

error: invalid module item.

Can someone help me in fixing this issue?

I corrected the example code to have input/output definitions. I still get compile errors at instantiation lines. — user2562153
– user2562153, Commented Jun 4, 2015 at 18:41
More discussion on this question asked here: verificationacademy.com/forums/systemverilog/… — dave_59
– dave_59, Commented Jun 4, 2015 at 21:13

Greg · Accepted Answer · 2017-12-18 21:10:25Z

1

`` a SysemVerilog feature. Is is not described in any Verilog LRM (I checked IEEE Std 1364-2001 and IEEE Std 1364-2005), therefore a Verilog Simulator does not need to support it.

Modern Verolog simulators do support SystemVerilog. Simply changing the file extension from .v to .sv should enables SystemVerilog support for that file. Many simulators also have a -sv compiler option, but be warned this makes all Verilog files treated as SystemVerilog (only a problem if there are variable names that are now SV keywords).

The IEEE Std 1800-2012 as good examples of using `` in § 22.5.1 `define

edited Dec 18, 2017 at 21:10

answered Jun 4, 2015 at 19:23

Greg

19.3k6 gold badges51 silver badges72 bronze badges

Sign up to request clarification or add additional context in comments.

2 Comments

user2562153 Over a year ago

How else can I make it work in pure Verilog 2001 format? Any other alternative way for enabling this feature? I cannot use -sv switch to treat this RTL as .sv.

Greg Over a year ago

You could use embedded Perl/Ruby/Python which I mentioned in answers to similar questions: see here, here, & here. This will require a running the Perl/Ruby/Python script to generate the .v file before compiling with the simulator.

Collectives™ on Stack Overflow

Verilog Parameterized macro usage

1 Answer 1

2 Comments

Your Answer

Linked

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

2 Comments

Your Answer

Sign up or log in

Post as a guest

Linked

Related