VHDL - array of std_logic_vectors convert into std_logic_vector

Question

INTENTION:

I am reading data from RAM on ZedBoard, the RAM consists of 32 bits long words so I use the following buffer

type mem_word   is array (0 to 127) of std_logic_vector(31 downto 0);
signal buffer_word   : mem_word;

but then, I would like to address data in a linear fashion, in an intermediary linear buffer

signal buffer_linear : std_logic_vector(4095 downto 0);
buffer_linear <= buffer_word; -- !!! PROBLEM

so I can easily address any bit in the buffer without recalculating the position in specific word (of the buffer_word).

QUESTION:

How do I get from array of std_logic_vectors into 1 long std_logic_vector ? Is there a way to avoid concatenating 128 words in a loop ? (something like above buffer_linear <= buffer_word;)

Paebbels · Accepted Answer · 2016-04-15 11:22:09Z

4

You need a function to convert from vector-vector to a 1-dimensional vector.

My following example uses the type name T_SLVV_32 to denote that it is a vector of vectors, wherin the inner vector is 32 bit long. (See my linked source file, for a true 2-dimensional STD_LOGIC matrix type called T_SLM). So T_SLVV_32 is equivalen to your mem_word type.

subtype T_SLV_32  is STD_LOGIC_VECTOR(31 downto 0);
type    T_SLVV_32 is array(NATURAL range <>) of T_SLV_32;

function to_slv(slvv : T_SLVV_32) return STD_LOGIC_VECTOR is
  variable slv : STD_LOGIC_VECTOR((slvv'length * 32) - 1 downto 0);
begin
  for i in slvv'range loop
    slv((i * 32) + 31 downto (i * 32))      := slvv(i);
  end loop;
  return slv;
end function;

Usage:

buffer_linear <= to_slv(buffer_word);

This function creates no logic, just wiring.
Note: Accessing all bits of a memory at once, prevents synthesis tools of inferring RAM or ROM memory blocks!

Source: PoC.vectors

See my vector package at GitHub for more examples on transforming vectors and matrices forth and backwards.

answered Apr 15, 2016 at 11:22

Paebbels

16.5k15 gold badges84 silver badges150 bronze badges

Sign up to request clarification or add additional context in comments.

3 Comments

Martin G Over a year ago

what is the condition under which the RAM block can be used ? Is there a limit to accessed bits at once ?

scary_jeff Over a year ago

@MartinG Your best bet is to look at your synthesis tools memory inference patterns. For example here xilinx.com/support/documentation/sw_manuals/xilinx2014_1/… page 95 and onward

user1818839 Over a year ago

The condition is likely to include that the read and write processes are both synchronous, i.e. clocked processes, since the BlockRam is a synchronous RAM - and that some upper limit (32 or 64) bits are read simultaneously.

Collectives™ on Stack Overflow

VHDL - array of std_logic_vectors convert into std_logic_vector

1 Answer 1

3 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

3 Comments

Your Answer

Sign up or log in

Post as a guest

Related