Using Verilog parameters in if else conditions

Question

Consider the following Verilog code.

parameter  C_SUB_WIDTH  = 2;
parameter  C_SUB_HEIGHT = 2;
parameter  BIT_DEPTH    = 12;

reg [5:0]  single_block_width;

always @ (*) begin
    if(BIT_DEPTH == 8) begin
        case({C_SUB_HEIGHT == 1, C_SUB_WIDTH == 1})
            2'b00:  single_block_width = 6'd16;
            2'b10:  single_block_width = 6'd16;
            2'b11:  single_block_width = 6'd24;
            default:single_block_width = 6'dx;
        endcase
    end
    else if(BIT_DEPTH == 10) begin
        case({C_SUB_HEIGHT == 1, C_SUB_WIDTH == 1})
            2'b00:  single_block_width = 6'd16;
            2'b10:  single_block_width = 6'd24;
            2'b11:  single_block_width = 6'd32;
            default:single_block_width = 6'dx;
        endcase
    end
    else if(BIT_DEPTH == 12) begin
        case({C_SUB_HEIGHT == 1, C_SUB_WIDTH == 1})
            2'b00:  single_block_width = 6'd24;
            2'b10:  single_block_width = 6'd24;
            2'b11:  single_block_width = 6'd40;
            default:single_block_width = 6'dx;
        endcase
    end
    else begin
        single_block_width = 6'dx;
    end
end

Since C_SUB_WIDTH, C_SUB_HEIGHT and BIT_DEPTH are all parameters, would this make single_block_width, a parameter too?

If not, then how can I make single_block_width a parameter and set its' value based on above mentioned parameters?

I am using Xilinx Vivado to synthesize the above code. (Its has to be able to synthesize)

Thank you.

BTW, it is bad for simulation to use an always @(*) with only parameters in the always block. Since the parameters never change, there is nothing for the block to be sensitive to, and the block never executes. SystemVerilog solves this with the always_comb construct which guarantees that it will execute the block at least once during time 0. — dave_59
– dave_59, Commented May 7, 2016 at 15:28

Prakash Darji · Accepted Answer · 2016-05-07 09:25:45Z

2

parameter [5:0] SINGLE_BLOCK_WIDTH = (BIT_DEPTH == 8) ? ((C_SUB_WIDTH == 0) ? ((C_SUB_HEIGHT == 0 ) ? 6'd16 : 6'd16) : 6'd24) 
                                 : ((BIT_DEPTH == 10) ? ((C_SUB_WIDTH == 0) ? ((C_SUB_HEIGHT == 0 ) ? 6'd16 : 6'd24) : 6'd32) 
                                   : (BIT_DEPTH == 12) ? ((C_SUB_WIDTH == 0) ? ((C_SUB_HEIGHT == 0 ) ? 6'd24 : 6'd24) : 6'd40));

Try this type of coding. It may have logical error but it is synthesise.

answered May 7, 2016 at 9:25

Prakash Darji

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