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I have a makefile in which I'm trying to set some variables which already exist in a bash script which I wrote called: set-vars.sh (it just contains variable names and values).

I'm using these variables in several other bash scripts. I need to also be able to use them in my makefile.

After a lot of researching and trying to figure out what is the best way to set variables from a bash script in makefile, I've found a way which works; which is as follows:

set-vars.sh:

# set vars
foo=FOO1
bar=BAR1
baz=BAZ1

# if a command line arg is given (e.g. foo) 
# echo value command line arg (e.g. echo $foo)

if ! [ -z ${1+x} ]; then echo ${!1}; fi

The magic here is the last line which echoes the value of a variable the name of which is provided in the command line argument, IF there is a command line argument. I call this script in the makefile and provide the variable name and use the echoed value to set the makefile variables.

Makefile:

.PHONY:  target1 target2 target3

export foo = $(shell sh set-vars.sh foo)

target1:
    @echo $(foo)

# ... other targets which reference $(foo) ...

This works, but it is probably a hacky way of doing it. I'm wondering if there is a more simple, elegant way to do what I want to do.

I've come across several similar questions and answers on StackOverflow but didn't find anything that works with my example. If there is an answer already which I missed, please point me to it.

Many thanks!

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4
  • You can't set the variables in the shell that calls make, or put them on the make command line? Commented Aug 17, 2016 at 21:41
  • Do other scripts need that if ! [ -z... line? Commented Aug 17, 2016 at 22:51
  • @Barmar, I can't put them on make command line because this makefile will be used by other people who may or may not be familiar with the inner workings of this makefile. I want to keep the calling of the makefile as simple as possible... but what do you mean by setting the variables in the shell that calls make? Sorry I'm not too proficient in shell scripting. Commented Aug 18, 2016 at 3:30
  • @Beta, no this line was added specifically for the makefile so I can set the variables in the makefile using the value which was echo'd from the bash script. Commented Aug 18, 2016 at 3:31

3 Answers 3

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You can define your variables in a file that can be sourced from your shell scripts and included from your Makefile:

$ cat vardef.txt
foo=FOO1
bar=BAR1
baz=BAZ1
$ cat set-vars.sh
source ./vardef.txt
echo "$foo $bar $baz"
$ sh ./set-vars.sh
FOO1 BAR1 BAZ1
$ cat Makefile
include vardef.txt
all:
    @echo "$(foo) $(bar) $(baz)"
$ make
FOO1 BAR1 BAZ1

Isn't it just wonderful when two languages partly use the same syntax?

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3 Comments

This looks promising... I will give it a try. Thanks!
Gave it a try. Works well with the Makefile, not so well with the shell scripts. Getting this: subtest.sh: line 3: source: vars.txt: file not found.
Did you try source ./vars.txt or source vars.txt?
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Not sure if it's less hacky, but you can "create" a file that can be included into Makefile. In runtime. Like this:

$(shell grep '=' vars.sh > /tmp/vars.tmp)
include /tmp/vars.tmp
$(shell rm /tmp/vars.tmp)

Replace the first line with something more sane.

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Comments

1

It is generally considered poor practice for build systems to depend on environment variables because if they do you suddenly have a reproducibility problem when the output depends not only on the command line but also on the state of environment variables.

Having warned you, all environment variables are accessible in make, e.g.:

user := ${USER} # ${USER} comes from the environment.
all :
    @echo ${user}

In other words, have a script that sets the environment variables and invokes make:

#!/bin/bash
export foo=FOO1
export bar=BAR1
export baz=BAZ1
exec make "$@"

Alternatively, you can have a shell script with export foo=FOO1 statements only. This turns out to be valid makefile syntax, so that you can do include set-vars.sh in your Makefile.

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3 Comments

This would work, but I need to be able to run make from the command line, not from a script. I need make to be able to get all the correct variables and values under the hood. Thereby creating a level of abstraction where the users don't have to do anything except run make install or whatever target they want to run without knowing what's inside the Makefile.
@tamjd1 Added an alternative solution for you.
Just noticed that @RenaudPacalet originally gave this advice.

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