i am trying to implement a bigger ram using block rams in my VERILOG code which has exceeded the limit of depth of that particular block ram in the device (i need a ram of depth 4500 and max depth of one block ram is 512). how to cascade block rams using attributes in my verilog code. thanks in advance
1 Answer
Given good synthesis tools, you might simply infer a large RAM without the need of technology-dependent attributes. So check your synthesis manual for your technology for inferring block ram. Typical mistakes over there would be to e.g. add a reset on the memory, which is not available in most technologies.
3 Comments
vlsi_user
i am using vivado to synthesize my code. and its taking so much of time to generate a bit file and in log i observed that the ram is being implemented in registers rather than in block ram. what should i do to implement my ram in block ram
Prashant
@vlsi_user the amount of time needed by the tools to synthesize, map and generate a bit file is generally dependent on the size of your design. Regarding the RAM being implemented as registers instead of Block RAMs, it would be helpful if you could post snippets of your code showing either the Block RAM module you have written or snippets of code where you are instantiating your RAM.
Wei Song
@vlsi_user the Block ram in fpga is different from SRAM in ASIC. That is to say, you need to allow 2 cycle delay rather than 1 to infer an FPGA block ram. Something like always @(posedge clk) begin addr_reg <= addr; rdata <= mem[addr_reg]; end