Syntax error in if statement in vhdl

Question

I am new to VHDL. I am trying out a code to find whether a bit vector is is even r not (using hamming weight of the bit vector). The code I wrote is:

entity hw_mod is
generic(
bits:integer  );
port (
inp : in std_logic_vector((bits-1) downto 0;
   cout : out std_logic );
end entity hw_mod

 architecture hw_arch of hw_mod is
begin

 process(inp)
 variable count : Integer:=0;

begin
    labelloop: for i in 0 to (bits-1) loop
                 if(inp(i)=='1') then
                   count:= count+1;
                         end if;
                      end loop;
                   if ((count mod 2)== '0') then
                       cout:=1;
                   else
           cout:=0;
           end if;
 end process;
   end hw_arch;

the error I keep getting is "near "=": syntax error in two places.

So I googled for "vhdl comparison operator" and the first result said equality is =, not ==. — melpomene
– melpomene, Commented Sep 24, 2016 at 18:14
I tried that earlier ,but the error I got was "near "=" : expecting == or + or - or & — Abhishek V. Pai
– Abhishek V. Pai, Commented Sep 24, 2016 at 18:46
Your question isn't a Minimal Complete and Verifiable example. As the non-VHDL guy notes "==" isn't a relational operator in VHDL (while "=" is). See IEEE Std 1076-2008 9.2.3 Relational operators. You're missing a closing paren in the inp port declaration subtype indication range, end entity hw_mod is missing a statement closing semicolon, count is an integer compare it to a decimal literal, use signal assignment for cout, and it's std_ulogic based (e.g cout <= '0'; not cout := 0;). You have superfluous parentheses in your if statement conditions. — user1155120
– user1155120, Commented Sep 24, 2016 at 19:00
count represents the '1's popcount of input, count mod 2 = 0 represents even parity (even numbers of '1's). In -2008: cout <= not (xor inp); (Thats a unary XOR (reduction) operator, an even number of '1's will produce a '1' on cout, it's an optimization of popcount looking at the LS bit). An array value (e.g. std_logic_vector) arithmetic ("+", count) would also be modular without a mod operator. — user1155120
– user1155120, Commented Sep 24, 2016 at 19:46
With your method count needs to be set to 0 before the for loop for repetitive process resumptions (when inp changes). — user1155120
– user1155120, Commented Sep 24, 2016 at 19:57

Philippe · Accepted Answer · 2016-09-26 15:58:20Z

1

Several problems. Use an editor that checks your syntax while you type.

Parentheses are not matched.
You are missing some semicolons,
you use C-style comparisons (== instead of =)
variable assignments where you need signals (:= instead of <=)

answered Sep 26, 2016 at 15:58

Philippe

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Comments

Stingray · Accepted Answer · 2016-09-26 13:00:36Z

I checked your code: - the generic was not ok
- cout is a signal, so it needs <=
- := is only for variables

It gives no errors, but still there are latches. Variables need to be initalized before using.

LIBRARY ieee;  
    USE ieee.std_logic_1164.all;  
    USE ieee.numeric_std.all;  
entity hw_mod is  
generic(  
    bits : integer range 0 to 3 := 3);   
port (  
    inp : in std_logic_vector((bits-1) downto 0);  
    cout : out std_logic );  
end entity hw_mod;  

architecture hw_arch of hw_mod is  
begin  
    process(inp)  
    variable count : Integer:=0;  
    begin  
        labelloop:   
            for i in 0 to (bits-1) loop  
                if(inp(i)='1') then
                    count:= count+1;
                end if;  
            end loop;  
            if ((count mod 2)= 0) then  
                cout <= '1';  
            else  
                cout <= '0';  
            end if;  
    end process;  
end hw_arch;

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