VHDL : error in converting std_logic_vector to integer

Question

I was writing a code in vhdl (xilinx) for a digital tachometer. While converting the std_logic_vector m1 to integer the following errors were shown by the compiler.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity tacho is
    Port ( A : in  STD_LOGIC;
           B : out  STD_LOGIC_vector (15 downto 0));
end tacho;

architecture Behavioral of tacho is
component counter
            port(
            clk: in std_logic;
            m: out std_logic_vector (4 downto 0));
end component;
signal m1 : std_logic_vector (4 downto 0); 
variable y: integer := 0;
variable z: integer := 0;           
begin
x: counter port map(A,m1);
y:= to_integer(unsigned(m1)); --error1:Syntax error near ":=". error2:Expecting type  void for <to_integer>.
z:= y * 60; --Syntax error near ":=".
B <= std_logic_vector(to_unsigned(z, 16));
end Behavioral;

I found in many websites that the syntax i wrote is correct. Please help!

A tachometer usually counts the number of events over some sampling interval. That's not apparent in your design. — user1155120
– user1155120, Commented Mar 27, 2017 at 19:04
Don't use variables... well, at least: not like this. Also it is not advised to use unconstrained integers in synthesis, as they will else expand to 32-bit values. — JHBonarius
– JHBonarius, Commented Mar 28, 2017 at 8:30

Morten Zilmer · Accepted Answer · 2017-03-27 18:05:34Z

2

Variables y and z can't be declared at architecture level. Use signals instead, and the signal assign <=, like:

...
  signal y : integer;
  signal z: integer := 0;           
begin
  x: counter port map(A, m1);
  y <= to_integer(unsigned(m1));
  z <= y * 60;
  B <= std_logic_vector(to_unsigned(z, 16));
...

Or simply combine it and avoid the intermediates y and z, like:

  ...
  x: counter port map(A, m1);
  B <= std_logic_vector(resize(60 * unsigned(m1), B'length));
  ...

answered Mar 27, 2017 at 18:05

Morten Zilmer

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Comments

user1155120 · Accepted Answer · 2017-03-27 18:45:48Z

A non-shared variable can only be declared in a process statement or subprogram. You could place your scaling code in a process:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tacho is
    port ( A:   in  std_logic;
           B:   out std_logic_vector (15 downto 0)
    );
end entity tacho;

architecture behavioral of tacho is
    component counter is
        port (
            clk: in  std_logic;
            m:   out std_logic_vector (4 downto 0)
        );
    end component;
    signal m1 : std_logic_vector (4 downto 0);
begin

x: counter port map (A, m1);

scaling:
    process (m1)
        variable y: integer := 0;
        variable z: integer := 0;
    begin
        y := to_integer(unsigned(m1));
        z := y * 60;
        B <= std_logic_vector(to_unsigned(z, 16));
    end process;
end architecture behavioral;

Or you could move your calculations to a subprogram:

architecture scaled of tacho is
    component counter is
        port (
            clk: in  std_logic;
            m:   out std_logic_vector (4 downto 0)
        );
    end component;
    signal m1 : std_logic_vector (4 downto 0);
    function scale(m1: std_logic_vector (4 downto 0); SIZE: natural := 16)
            return std_logic_vector is
        variable y: integer;
        variable z: integer;
    begin
        y := to_integer(unsigned(m1));
        z := y * 60;
        return std_logic_vector(to_unsigned(z, SIZE));
    end function;
begin

x: counter port map (A, m1);
scaled_output:
    B <= scale(m1);
end architecture;

Both of these analyze.

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