Verilog select bit depending on input

Question

I am writing a behavioral verilog module where a different bit is selected based upon one of the input variables. I wrote the following code to reference the 3-S position in the D vector:

module Part4(input [3:0] D, input [1:0] S, output F);
    always @(D, S)
        F = D[3-S];
endmodule

This gives the following errors: "ERROR:HDLCompilers:247 - "Part4.v" line 5 Reference to scalar wire 'F' is not a legal reg or variable lvalue ERROR:HDLCompilers:44 - "Part4.v" line 5 Illegal left hand side of blocking assignment"

How do I go about selecting a different bit based upon the input S?

Patrick Roberts · Accepted Answer · 2018-02-25 22:37:55Z

1

If F is a wire, then you can't assign to it inside an always @ block. Either change it to a reg, or do the assignment outside of an always @ block like this:

module Part4(input [3:0] D, input [1:0] S, output F);
    assign F = D[3-S];
endmodule

answered Feb 25, 2018 at 22:37

Patrick Roberts

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2 Comments

user2417339 Over a year ago

Ok thanks! Out of curiosity how will this circuit be synthesized? Like is it actually going to create 2 wires somewhere that send the signal for what bit to read or is it more complicated than that?

Patrick Roberts Over a year ago

Both approaches will result in the same synthesis, since there were no latches in always @(D, S), but changing F to a wire will result in faster compilation since there's less optimization needed. To answer your question, it's probably just a typical multiplexer that switches on S, but if you want to confirm you should look at the synthesis diagram yourself depending on the tools you have.

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