Verilog conditional hardware based on parameter value

Question

Is it possible to create conditional hardware in Verilog depending on the value of a parameter? Something like this

module test #(
 parameter param = 1
)(
  input wire clk
);

reg[3:0] counter = 0;

always @(posedge clk) begin
  `ifdef (param == 0)          // <-----
    counter <= counter + 1'b1;
    // ... more hardware here
  `else
    counter <= counter - 1'b1;
    // ... a different hardware here
  `endif
end

endmodule // test

EDIT:

I wanted to mention that both answers given by Serge and Unn give a solution to the implementation I was looking for. See the comments to the answers for more details.

Serge · Accepted Answer · 2018-08-28 16:12:23Z

3

actually there are generate blocks which were invented for this reason:

module test 
  #(parameter param = 1)
   (input wire clk);

   reg [3:0]  counter = 0;

   generate
      if (param == 0) 
        always @(posedge clk) begin
           counter <= counter + 1'b1;
           // ... more hardware here
        end
      else
        always @(posedge clk) begin
           counter <= counter - 1'b1;
           // ... a different hardware here
        end
   endgenerate
endmodule // test

answered Aug 28, 2018 at 16:12

Serge

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Comments

Unn · Accepted Answer · 2018-08-28 16:07:13Z

3

Yes, you can condition on parameters. Just use them as you would condition on anything else (though you can also use them outside procedural blocks to condition entire instantiations if needed):

module test #(parameter param = 1)
  (
  input wire clk
  );

  reg[3:0] counter = 0;

  always @(posedge clk) begin
    if (param == 0) begin
      counter <= counter + 1'b1;
    end
    else begin
      counter <= counter - 1'b1;
    end
  end

endmodule // test

answered Aug 28, 2018 at 16:07

Unn

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4 Comments

dave_59 Over a year ago

Also note that since param is a constant, the unused branch gets optimized away

SebastianRV Over a year ago

I thought of this, but I didn't go for it because both cases are going to be created in hardware. Under every case I would like to create more than just a counter increment/decrement. I wanted to avoid using resources which are never going to be used if the value of the parameter is zero. The solution proposed by Serge seems to implement what I was looking for.

Unn Over a year ago

@SebastianRV Serge's answer is fine as well, though by bringing out the parameter you will have to include a bunch of redundant code in any branches from param (like the always @(posedge clk)). Such redundancies can lead to bugs so be careful. As dave_59 noted, since param is compile time constant, the unused branch in each instantiation will be optimized out leading to no additional hardware. I forgot to mention that explicitly in my answer.

SebastianRV Over a year ago

Thanks for the comments. I did notice later during implementation that the compiler does indeed optimize the code away and implements only the active branch. In my implementation I ended up doing a combination of both techniques---the generate proposed by Serge and the if-then-else inside always proposed by Unn---for different cases.

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