Accessing array elements using std_logic_vector (VHDL)

Question

Please see the code below:

....
port(
the_input: in std_logic_vector(0 to 3));
...
type dummy_array is array (0 to 2) of std_logic_vector (0 to 7);
signal ins_dummy: dummy_array := ( 8x"1",  8x"2", 8x"3");
...

Now I want to access the elements of this array using bits the_input(0 to 1). How can I do this? as I know array accepts integers as arguments, but this input is std_logic. I tried many solution available on different forums but nothing seems to be working. For example when I apply this: to_integer(unsigned(the_input(0 to 1))), result is zero.

What is happening? I don't know. Any suggestions?

Please provide a minimal reproducible example. The unknowns here include the value of the_input, the purported entity's context clause, where the expression to_integer(unsigned(the_input(0 to 1))) is being evaluated at what time in the simulation, and what context the result value zero is obtained. — user1155120
– user1155120, Commented Sep 19, 2018 at 21:13

F Gonc · Accepted Answer · 2018-09-19 18:14:54Z

2

Using the small testbench below, I was able to access elements of the array using the method you mentioned -> some_array(to_integer(unsigned(some_signal))).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;   
use std.textio.all;
use ieee.std_logic_textio.all;

entity test is
end entity test;

architecture behav of test is
    signal the_input : std_logic_vector(0 to 3);
    signal test_sig  : std_logic_vector(7 downto 0);
    type dummy_array is array(0 to 2) of std_logic_vector(7 downto 0);
    signal ins_dummy : dummy_array := (x"01", x"02", x"03");

begin

    test_sig <= ins_dummy(to_integer(unsigned(the_input)));

    process
    begin
    wait for 1 ns;
    the_input <= "0000";
    wait for 1 ns;
    the_input <= "0001";
    wait for 1 ns;
    the_input <= "0010";
    end process;
end architecture behav;

However, this is a simulation and a synthesizer may complain because the range of the port the_input is larger than the number of possible array options. You might have to add logic to ensure that the array indices which are "out of bounds" cannot be accessed. Hope that helps. Possibly try:

test_sig <= ins_dummy(to_integer(unsigned(the_input))) when (the_input < 3) else
            others => '0';

answered Sep 19, 2018 at 18:14

F Gonc

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1 Comment

TRoa Over a year ago

Thank you sir. I really appreciate the time you spent in testing my code. I learned one thing from this experiment, and the thing is: be very very careful with "downto" and "to" notation. This might bite really hard, as in my case. I was mixing this notation throughout my code, not knowing that one is like [7:0] and the other is [0:7], and hence the confusion and all that. Thanks again. Cheers.

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