Compute processing time Verilog using simulation and using FPGA

Question

New to fpga world, i wrote a verilog HDL program for nxn matrix multiplication and now i want to compare time between FPGA and CPU/GPU. I get the execution time on CPU/CPU by using time.time() in python or using profiling. How do i achieve the same thing in vivado simulation (how to use same hardware specs of basys3 in simulation)? the Basys 3 (Hardware) is yet to be delivered.

Is there a way to calculate a metric which is same for both the worlds ? Time or clock cycles .. ?

Thanks for your help.

Oldfart · Accepted Answer · 2020-04-04 07:26:46Z

0

You can measure how many clock cycles it takes to finish the calculation.^**

Unfortunately that is not enough.
The simulation is artificial. You can run it at any speed. If you want, you can use a 500GHz clock in simulation, which you know is not real. You need to synthesize the code and see what the tool tells you the maximum speed is which the code can run at. Then use that clock speed with the cycles from the simulator to calculate the time it takes to finish.

That is fine in theory.
Practically you also are going to need to get the data to and from the FPGA. If you can't do that fast enough your I/O is the bottleneck, not the actual matrix calculation.

^**_{Use the cursor to measure the time of the simulation. Divide that by the time of one clock cycle.}

answered Apr 4, 2020 at 7:26

Oldfart

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2 Comments

Serge Over a year ago

My guess is that OP cares about wall time of emulation and simulation. OP just needs to have a good stopwatch and make sure that the test in both worlds does the same job :-).

Jay Desai Over a year ago

I am trying to find out the propagation delay of just calculating matA*matB operation, doing the behavioral simulation gives the correct output but post synthesis shows more than 100% IO utilization and the output is always Z... (trying to compare np.dot(mata,matb) vs fpga)

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