Why am I getting error while using if statement with assign in Verilog?

Question

module latch(clk,d,q);
    input clk,d;
    output q;
    
    if(clk==1)
    assign q = d;
endmodule

Why am I getting error in the above code?

Can you add the details of the error in your question? Maybe a screenshot? — Thomas
– Thomas, Commented Aug 8, 2020 at 15:30
Error: Peak virtual memory: 4690 megabytes Error (10170): Verilog HDL syntax error at latch.v(4) near text: "if"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. — Surabhi T S
– Surabhi T S, Commented Aug 9, 2020 at 10:44

Light · Accepted Answer · 2020-08-08 06:01:36Z

4

if is not a top level block inside a module. It should be used inside an always, or initial (if for simulation purposes) block, or other legal blocks. While assign is. (generate is not taken into consideration, for simplicity)

I guess what you want to achieve is:

module latch(clk, d, q);
input clk, d;
output q;
reg q;
always@(*)begin
  if(clk)begin
    q = d;
  end
end

edited Aug 8, 2020 at 6:01

answered Aug 8, 2020 at 5:54

Light

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2 Comments

Surabhi T S Over a year ago

So, I can't use any control flow statements in conjunction in "assign"?

gatecat Over a year ago

You can use ?: like assign q = clk ? d : q; but not all tools will be happy with this.

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