Passing a varying number of macro arguments as a string in System Verilog

Question

I have an existing code that uses some macro definitions in order to display messages from my test cases. I want to change the implementation of these macros, however, as these macros are extensively used in already existing testcases, I am looking to reimplement their functionality without having to modify how the macros are used.

Currently the macros are defined as such:

`define My_Info         $write("INFO:"); $display
`define My_Error        $write("ERROR:"); $display

In the testcases, example calls of these macros include:

`My_Info("This is an info message with arguments %0d, %0d, and %0d", var1, var2, var3);
`My_Info("My_ID",  $psprintf("ID    : %s", var4));
`My_Error("Failed to open file: %s ", fname);

Currently $display, displays the messages in the brackets.

What I want to do is to define the macros in a way that these messages in the brackets of the macro calls could be passed as a string argument to a function (for example the function my_msg(msg) where msg is a string and my_msg is a function that formats and returns this string to the log file.

My issue is, because in the testcases the macro calls have varying number of arguments as seen in the example above, I am not sure how to define the macros in a universal way.

Currently my solution is to define the macros like:

`define My_Info(string=" ", var1= , var2= , var3= , var4= )       my_msg($sformat(s,var1, var2, var3, var4)

But this relies on a finite number of arguments (in this case 5).

Is there a more elegant way of doing it?

dave_59 · Accepted Answer · 2021-04-08 17:37:12Z

2

You can workaround the lack of varying numbers of macro arguments by requiring an extra set of ()'s.

module top;
  
  `define my_error(msg) begin $error({"My ID:",$sformatf msg}); end
  
  int a,b;
  
  initial begin
    `my_error( ("hello") )
    `my_error( ("A = %0d B = %0d", a,b) )
  end
endmodule

answered Apr 8, 2021 at 17:37

dave_59

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2 Comments

Rama Krishna Meda Over a year ago

Hi Dave, Is this support do we have in verilog-2005 also ?

dave_59 Over a year ago

@RamaKrishnaMeda, Macros are poorly defined in Verilog. This works in the Verilog-mode of tools that also support SystemVerilog.

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