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I have a conceptual (ish) question that I can't understand. I have an assignment and it is telling me to choose which of the following 4-bit binary (2's complement) additions will result in overflow. The following are:

  • A. 1011+1001
  • B. 1100+1101
  • C. 0111+1000
  • D. 1010+0110

For A, I got 10100, for B, I got 11001, for C, I got 1111, and for D, I got 10000.

There is only one answer apparently, but A, B, and D all produce an overflow. They end up in 5-bits rather than 4-bits. When I asked the instructor if he meant to say which one of these do NOT produce an overflow but he said that the question is correct. He gave me this hint:

For 4-bit unsigned numbers, overflow means that the sum of 2 numbers can't be represented in unsigned bits. For 4-bit 2's complement, overflow is when the sum of two numbers cannot be represented in 4-bit 2's complement.

This however did not help me, because it is already my understanding - for A, B, D, the sum is unable to be represented in 4-bit 2's complement. What am I doing wrong?

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For twos-complement representation, the top bit of the representation has a negative value: -(2k-1) rather than 2k-1 for a k bit representation. This means that when you add them, you can't just look at the carry out of the top full-adder (the 5th bit output in your examples) -- you need to compare it against the carry in to the top bit, and you only get an overflow if the two carries are different. What's actually happening here is that you are subtracting the carry in to the top bit, rather than adding it.

So to look at example B in more detail:

first value     1 1 0 0
second value    1 1 0 1
carry value    1 1 0 0
result          1 0 0 1

So in this case, the carry in to the sign bit is the same as the carry out, so there is no overflow -- the 4 bit 2s complement result of 1001 is the correct.

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You must disregard the fifth bit. We are calculating modulo 16, just with 4 bits.

  • A -5 + -7 = -12 but result 4
  • B -4 + -3 = -7
  • C 7 + -8 = -1
  • D -6 + 6 = 0

So overflow happens in A.

The fifth bit is absent. It would in a processor be a something like an overflowish carry flag.

Overflow can only happen when the signs of both terms are the same: sign1 xor sign2 = 0. And the result has a different sign. In a processor one normally have a sign flag and such an overflow flag.

Logical: two negative numbers below -8, or two positive numbers above 7.

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