Is it okay to use module's output as an input of submodule in Verilog?

Question

Hi I'm neophyte in Verilog and I have some question about designing module.
Is it okay to use top module's output as an input of submodule (Taking both module as sequentional logic)?
To my intuition about flip-flop, it seems to be okay but I'm not sure if this kind of approach is acceptable in verilog coding (anyway in logical or conventional). Should this kind of coding be avoided ?

module sample_top(
    input a,
    input b,
    input c,
    output d,
    output e
    );
    
    //sequential
    sample_submodule_1 SAMPLE_SUBMODULE_1(
        //input of submodule
        .A(a),
        .B(b),
        //output of submodule
        .D(d)
        );

    //sequential
    sample_submodule_2 SAMPLE_SUBMODULE_2(
        //input of submodule
        .C(c),
        .D(d),
        //output of submodule
        .E(e)
        );

Thanks for your answer.

Thanks!!, I didn't tried it yet since my total code is pretty big and incomplete yet. I just wanted to make sure if that kind of approach is available. You know, figuring out your intrinsic misunderstanding after you spend a lot of time trying it will be bit sad. In addition I was also curious if that kind of recursivity is somewhat acceptable in verilog society. — won5830
– won5830, Commented Nov 30, 2021 at 15:21

dave_59 · Accepted Answer · 2021-11-30 15:57:06Z

2

The Verilog language does not really care about port directions. Hierarchy is just for creating namespaces and containers of behaviors. A port connection becomes a symbolic naming of a and A to a single wire object.

Other HDLs like VHDL do place restrictions on reading the values outputs. The difference between these HDLs is an artifact of how these languages resolve multiple drivers (which would take too much time to get into here). In Verilog you can see the effect of multiple driver resolution if one side of the port is a variable(reg), and the other side is a wire. Only the wire side of the port gets to see the resolved value of multiple drivers.

answered Nov 30, 2021 at 15:57

dave_59

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ToTamire · Accepted Answer · 2021-11-30 19:13:42Z

Output signals should not be referenced. It's recommendation (best practice). Many professional linters tread it as warning or notice.

Direct connection of output and submodule output is ok (your submodule 1).
Direct connection of output and submodule input is violation (your submodule 2).
Direct connection of output and function return is ok.
Direct connection of output and function input argument is violation.
Direct connection of output and task output argument is ok.
Direct connection of output and task input argument is violation.
Other references to output port are violation.

For example:

module SOME_MODULE(
    clk,
    rstn,
    a,
    b,
    y
);

    input clk;
    input rstn;
    input [3 : 0] a;
    input [3 : 0] b;
    output reg [5 : 0] y;

    always @(posedge clk or negedge rstn) begin
        if (~rstn)
            y <= 5'd 0;
        else
            y <= y + a + b;  // Reference to output port detected
    end

endmodule

Should be described as:

module SOME_MODULE(
    clk,
    rstn,
    a,
    b,
    y
);

    input clk;
    input rstn;
    input [3 : 0] a;
    input [3 : 0] b;
    output [5 : 0] y;

    reg [5 : 0] y_reg;
    assign y = y_reg;

    always @(posedge clk or negedge rstn) begin
        if (~rstn)
            y_reg <= 5'd 0;
        else
            y_reg <= y_reg + a + b;
    end

endmodule

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