How to assign all inputs and outputs to an array?

Question

in my SystemVerilog module, I want to have all inputs in one single array and all outputs in another array.
The assumption is that the number of input and outputs are the same, an the bus assignements are in the same order in the input/output list. Background is, that I will generate the code automatically from a register/pin-list with several hundred named input/output pins.

I achieved the assignements in the below code.

Currently the output assignement only works with one assignement per output-pin/bus. What I actually want is an one-liner as indicated in the commented assignement (last line).

Any idea how to do this ?

    module sv_multipincheck (in1, in2, inXY, out1, out2, outXY );
    //The input and output definitions
    input real in1, in2[3:0] , inXY;
    output real out1, out2[4:1], outXY;
    
    //creating the input array
    real inArray [0:5];
    assign inArray = {in1, in2[3:0], inXY};
    
    //creating the output array
    real outArray [0:5];
    assign out1 = outArray[0];
    assign out2 = outArray[1:4];  //reversed order !!!
    assign outXY = outArray[5];
    //assign [out1, out2, outZ] = '{outArray[0], outArray[1:4], outArray[5]} ;   <-- this is what I actually want 
    ...

If this is automatically generated code, why do you care if it is one assignment per pin? Also, there is no way to reverse an array of reals in a single expression. — dave_59
– dave_59, Commented Jan 21 at 22:59
@dave_59 yes - since it is automated code, it does not matter much - it is just a question of readability and it would have been "nice" to have a kind of vector assignement as indicated in the last commented line. — HWe
– HWe, Commented Jan 22 at 14:07
@toolic not a problem - only a question if it is possible to do something like "assign <output-list> = <signal-list>", instead of "assign output1=signal1, output2=signal2, ..." — HWe
– HWe, Commented Jan 22 at 14:17

dave_59 · Accepted Answer · 2025-01-22 20:28:44Z

0

The problem is array concatenation ({} without the ') only work on the RHS of an assignment, and only when in the context of an assignment to a specific array type. Assignment patterns ('{} with the ') only work in the context a specific array type.

The one-liner you are trying to construct has no specific type on either side of the assignment.

And you cannot use the pack/unpack streaming operator or bitstream casting since these are non-integral real types, not bit-stream types.

edited Jan 22 at 20:28

answered Jan 22 at 16:59

dave_59

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