HDL Coder can generate fully portable, platform-independent VHDL or Verilog code from a MATLAB function or Simulink model that you can use with any FPGA device. Depending on your specific needs for automation, integration and interfacing, you have several options to choose from:
Option 1: Manual Integration of HDL Code
You can generate standalone VHDL or Verilog code from your MATLAB or Simulink algorithm, as shown in the following link:
You can then manually integrate the generated HDL code into your HDL tool and FPGA project.
Option 2: Automate Tasks with HDL Workflow Advisor "Generic ASIC/FPGA" workflow
HDL Workflow Advisor enables you to automate the tasks of generating HDL code from your MATLAB or Simulink algorithm, verifying the HDL code, as well as initiating synthesis, implementation, and timing analysis through integration with supported HDL tools (Xilinx Vivado, Xilinx ISE, Intel Quartus, Microchip Libero). For basic examples, see:
- HDL Code Generation and FPGA Synthesis from Simulink Model
- Basic HDL Code Generation and FPGA Synthesis from MATLAB
Refer to Generic ASIC/FPGA Hardware to see if your FPGA device family is supported with the "Generic ASIC/FPGA" workflow in HDL Workflow
Option 3: Generate Board-Independent IP Cores with HDL Workflow Advisor "IP Core Generation" workflow
An intellectual property core – often referred to as IP core – is a reusable HDL component. You can use the "IP Core Generation" workflow in HDL Workflow Advisor to generate board-independent IP cores from a MATLAB function or Simulink model. Supported HDL tools are Xilinx Vivado, Intel Quartus, and Microchip Libero:
- Custom IP Core Generation
- Generate Board-Independent HDL IP Core from Simulink Model for "Generic Xilinx Platform" or "Generic Intel Platform"
- Generate Board-Independent HDL IP Core from Simulink Model for "Generic Microchip Platform" (R2022b+)
- Generate Board-Independent HDL IP Core from MATLAB
This IP Core can then be added to the IP Core Repository in your HDL tool.
Option 4: Create a Custom Hardware Platform through Board Definition & Custom Reference Design
To enable faster design iterations and automatic deployment, you can create a custom reference design for your board in the HDL tool, and register it in MATLAB. See the following examples in our documentation:
- Board and Reference Design Registration System
- Define Custom Board and Reference Design for Zynq Workflow
- Define Custom Board and Reference Design for Intel SoC Workflow
- Define Custom Board and Reference Design for Microchip Workflow
You can then use HDL Workflow Advisor or Simulink Toolstrip (R2023b+) to have the IP core automatically integrated into your reference design and generate a bitstream in one go.
Option 5: Enable full support for your SoC device
If your board is an SoC device, and your goal is to not only target the FPGA hardware part, but also the processor software part, this is what we call "Hardware-Software Co-Design" or "SoC workflow":
There is a way to add support for custom SoC devices that you can develop yourself:
However, this task requires a deeper understanding of hardware and software engineering:
Further Assistance
Most of the above tasks, such as manual relocation and integration of generated HDL code or IP cores into an HDL tool, or creating a custom reference design, is outside the scope of MathWorks Technical Support.
MathWorks Consulting Services may be able to assist with these tasks: https://www.mathworks.com/services/consulting.html
