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answers

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Can I generate HDL Code for models with Xilinx System Generator blocks?

Asked by MathWorks Support Team on 8 Apr 2020

Latest activity Edited by MathWorks Support Team on 10 Nov 2025 at 11:49

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design External Component Interfaces

1

answer

2 votes
381 views

Which versions of Vivado are supported with which release of HDL Coder?

Asked by MathWorks Support Team on 16 Apr 2020

Latest activity Edited by MathWorks Support Team on 29 Sep 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
4 views

Why do I receive the message "No matching files were found" in HDL Workflow Advisor Step 4.2 "Build FPGA Bitstream"?

Asked by MathWorks Support Team on 21 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

Find Documentation, Examples and more on HDL Coder in Help Center

1

answer

0 votes
50 views

Troubleshooting connection issues with Xilinx Zynq platform

Asked by MathWorks Support Team on 3 Jul 2018

Latest activity Edited by MathWorks Support Team on 4 Mar 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

PDF Documentation for "Deep Learning HDL Toolbox Support Package for Intel / Xilinx FPGA and SoC Devices"

Asked by MathWorks Support Team on 14 Oct 2020

Latest activity Edited by MathWorks Support Team on 24 Dec 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

1 vote
18 views

Which Xilinx Vivado edition do I need to install for use with HDL Coder, HDL Verifier, or other HDL-related toolboxes?

Asked by MathWorks Support Team on 16 Apr 2020

Latest activity Edited by MathWorks Support Team on 24 Jan 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

Find Code on HDL Coder in File Exchange

1

answer

0 votes
0 views

Is the Filter Design HDL Coder optimized for specific targets?

Asked by MathWorks Support Team on 27 Jun 2009

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
10 views

How do I deploy an ARM software executable from a Simulink model to my Zynq board to run in standalone mode? And how can this exectuable be auto-run on startup?

Asked by MathWorks Support Team on 30 Jul 2019

Latest activity Edited by MathWorks Support Team on 24 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
21 views

How can I use a custom board with the Zynq workflow provided by MATLAB/Simulink?

Asked by MathWorks Support Team on 17 Jul 2021

Latest activity Edited by MathWorks Support Team on 7 Jun 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

When I right click on a Xilinx System Generator block in Simulink, why do I get errors in MATLAB?

Asked by MathWorks Support Team on 1 Feb 2019

Latest activity Edited by MathWorks Support Team on 15 Sep 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

Is it possible to import VHDL code into Simulink?

Asked by MathWorks Support Team on 27 Mar 2025

Latest activity Edited by MathWorks Support Team on 5 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder

1

answer

0 votes
17 views

How can I create a custom Linux image for my custom board to use the Zynq workflow or Intel SoC workflow with MATLAB/Simulink?

Asked by MathWorks Support Team on 17 Jul 2021

Latest activity Edited by MathWorks Support Team on 8 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
0 views

Why do I encounter an error message when I attempt to generate code for a Xilinx System Generator Subsystem?

Asked by MathWorks Support Team on 13 Dec 2016

Latest activity Answered by MathWorks Support Team on 9 Jan 2017

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Why does the NCO block in Signal Processing Blockset perform poorly in HDL synthesis when using HDL Coder (R2009b)?

Asked by MathWorks Support Team on 29 Mar 2013

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
2 views

Why do I get an error about a missing "thirdpartytools_win64.xml" file when I try to build my model for Xilinx Zynq platform?

Asked by MathWorks Support Team on 21 Jul 2016

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why am I getting a "SD card is read-only" error during hardware setup for HDL Verifier Support Package for Xilinx FPGA Boards?

Asked by MathWorks Support Team on 10 Jan 2024

Latest activity Answered by MathWorks Support Team on 19 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

Why do IP repositories for HW/SW Co-design fail to be found?

Asked by MathWorks Support Team on 6 Apr 2020

Latest activity Edited by MathWorks Support Team on 1 Apr 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

1 vote
1 view

Is it possible to get the source code for the Linux kernel that MathWorks uses to create the images for the Zynq support packages?

Asked by MathWorks Support Team on 8 Feb 2021

Latest activity Edited by MathWorks Support Team on 21 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
5 views

Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?

Asked by MathWorks Support Team on 22 Aug 2025

Latest activity Commented on by Kiran Kintali on 29 Aug 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
10 views

How do you generate HDL code for the Artix-7 family of boards? What is the recommended workflow for this?

Asked by MathWorks Support Team on 7 Jun 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Do I have to install a third-party synthesis tool to use HDL Coder?

Asked by MathWorks Support Team on 30 Mar 2021

Latest activity Edited by MathWorks Support Team on 1 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
18 views

Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

Asked by MathWorks Support Team on 17 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

How do I use unsupported synthesis tool versions with Deep Learning HDL Toolbox?

Asked by MathWorks Support Team on 5 Oct 2023

Latest activity Edited by MathWorks Support Team on 19 Feb 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
2 views

Why is not the return type of BITGET function uint8 in MATLAB 7.5 (R2007b)?

Asked by MathWorks Support Team on 27 Jun 2009

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder

1

answer

0 votes
4 views

How do I reduce resource utilization for an AXI4-Stream interface generated using HDL Coder?

Asked by MathWorks Support Team on 3 May 2021

Latest activity Answered by MathWorks Support Team on 3 May 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
8 views

Zynq workflow: Software interface model build fails due to error regarding missing "iio.h" file

Asked by MathWorks Support Team on 19 Jan 2022

Latest activity Answered by MathWorks Support Team on 20 Jan 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
7 views

Are Digilent Zybo boards supported for the Zynq workflow with HDL Coder & Embedded Coder?

Asked by MathWorks Support Team on 20 Apr 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
12 views

How can I use HDL Coder with an unsupported or custom FPGA board?

Asked by MathWorks Support Team on 28 Jan 2022

Latest activity Edited by MathWorks Support Team on 17 Jul 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
29 views

Why do I get the Vivado error message "Specified part could not be found" during IP Core Generation with HDL Workflow Advisor or SoC Builder?

Asked by MathWorks Support Team on 26 Jul 2023

Latest activity Edited by MathWorks Support Team on 12 Feb 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why does "Monitor and Tune" fail even though I built and compiled my code successfully with a precompiled shared library using MATLAB Coder?

Asked by MathWorks Support Team on 2 Nov 2023

Latest activity Answered by MathWorks Support Team on 2 Nov 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
8 views

Why does HDL code generation give errors when variable-sized variables are used?

Asked by MathWorks Support Team on 13 Aug 2025

Latest activity Answered by MathWorks Support Team on 18 Aug 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
1 view

Why do I receive the error "unable to allocate delays to compensate for the N delays introduced by BLOCK in native floating point mode"?

Asked by MathWorks Support Team on 4 Feb 2019

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
10 views

Do the "ADC/DAC Interface" reference designs support Vivado 2022.1 or later?

Asked by MathWorks Support Team on 24 May 2023

Latest activity Edited by MathWorks Support Team on 13 May 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Can I have levels of syntax highlighting for the HDL code opened in the MATLAB Editor in MATLAB 7.6 (R2008a)?

Asked by MathWorks Support Team on 8 Jan 2010

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

2

answers

0 votes
0 views

Do Enabled Subsystems use multiplexers in generated HDL code?

Asked by MathWorks Support Team on 10 Dec 2021

Latest activity Edited by Bharath Venkataraman on 13 Dec 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
0 views

How can I set properties such as Verilog Include Directories in the FILWIZARD of HDL Verifier 4.1 (R2012b)?

Asked by MathWorks Support Team on 11 Apr 2013

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

How can I troubleshoot UDP communication issues between Simulink and a Zynq SoC (Zedboard) in MATLAB R2024b?

Asked by MathWorks Support Team on 27 Aug 2025

Latest activity Answered by MathWorks Support Team on 27 Aug 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

Can I define customized Bus Data Types as input data types to HDL Coder DUT?

Asked by MathWorks Support Team on 31 Jan 2019

Latest activity Edited by MathWorks Support Team on 18 Aug 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Is there a block that captures HDL memory read/write operations in Simulink?

Asked by MathWorks Support Team on 27 Jun 2009

Latest activity Edited by MathWorks Support Team on 16 Oct 2023

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
5 views

Incorporate External HDL Code into Simulink Model

Asked by MathWorks Support Team on 13 Jun 2018

Latest activity Answered by MathWorks Support Team on 20 Jun 2018

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

2

answers

0 votes
5 views

When using the HDL Workflow Advisor, why do I get errors in Task 1.2 that mention "Dot indexing is not support for variables of this type"?

Asked by MathWorks Support Team on 18 Sep 2019

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

In R2018a, how can I force HDL Coder to generate HDL code for a lookup table to use RAM or Block RAM?

Asked by MathWorks Support Team on 16 Aug 2018

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
1 view

Why do I get output of all zero values from my generated model using HDL Coder R2017b?

Asked by MathWorks Support Team on 26 Dec 2017

Latest activity Answered by MathWorks Support Team on 11 Jan 2018

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
2 views

Why is it during balancing delays of the Simulink model that the added blocks do not include the initial condition of the already existing delay block?

Asked by MathWorks Support Team on 15 Jun 2020

Latest activity Edited by MathWorks Support Team on 27 Sep 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
3 views

Using HDL Coder, how can I do partial streaming of a MATLAB loop?

Asked by MathWorks Support Team on 9 Oct 2018

Latest activity Edited by MathWorks Support Team on 29 Feb 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
10 views

Why were the "Linear" and "Math" HDL architectures removed from the Divide and Reciprocal blocks in favor of "ShiftAdd"?

Asked by MathWorks Support Team on 8 Jul 2025

Latest activity Edited by MathWorks Support Team on 4 Aug 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design Model Design User-Defined MATLAB Functions

2

answers

0 votes
15 views

How are generics supported in HDL Coder?

Asked by MathWorks Support Team on 20 Dec 2017

Latest activity Edited by MathWorks Support Team on 19 Oct 2021

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design Model Compatibility Checks

1

answer

0 votes
2 views

Why do I get an error related to linked subsystems in HDL Workflow Advisor?

Asked by MathWorks Support Team on 31 Aug 2022

Latest activity Answered by MathWorks Support Team on 31 Aug 2022

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
171 views

How to resolve "This program is blocked by group policy" errors?

Asked by MathWorks Support Team on 20 Sep 2024

Latest activity Edited by MathWorks Support Team on 26 Feb 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
0 views

Can I use Simulink HDL Coder 1.5 (R2009a) on my Windows 64-bit machine?

Asked by MathWorks Support Team on 20 Jun 2011

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder

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