HDL-Coder: initialization of internal VHDL-signals

Question

Dennis Kaupmann am 29 Mär. 2018

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https://de.mathworks.com/matlabcentral/answers/391378-hdl-coder-initialization-of-internal-vhdl-signals

Beantwortet: Kiran Kintali am 16 Jul. 2023

Hello,

I've got a question regarding the VHDL-code generation of the HDL-Coder. I have a Simulink Model from which I generate VHDL-Code. This VHDL-Code has lots of internal signals corresponding to the signal-lines of the simulink model. Unfortunately these signals are not initialized with any value in VHDL (i.e.

SIGNAL In_signed : signed(31 DOWNTO 0);

hence simulation with an hand-written Testbench is noch working out as all internal signals are marked with 'X' (Forcing Unknown).

Is there a way to automatically initialize the internal signals with zero / others initial values in the corresponding fixpoint representation like

SIGNAL In_signed : signed(31 DOWNTO 0) := (others => '0');

Thanks for your help

Dennis