Issue to make log10 hdl code by using hdlcoder

2 visualizaciones (últimos 30 días)
satish guruma
satish guruma el 9 de Feb. de 2018
Editada: satish guruma el 9 de Feb. de 2018
Deal All,
I'm currently making the log hdl code by using hdlcoder.
and I've referred with exp-example of MATLAB and I just modify exp to log10.
but I came across the below error, might be MATLAB does not support log10.
### Candidate function not provided for approximation object for 'log10'. Setting the 'CandidateFunction' property automatically.
I think log function be able to make to HDL code as well.
But log10 is not.
Would you please help and give any hints to make a log10 HDL code?
clear all
clc
clear design_name testbench_name fxpCfg hdlcfg interp_degree
design_name = 'mlhdlc_replacement_exp';
testbench_name = 'mlhdlc_replacement_exp_tb';
%hsetupedatoolsenv();
design_name = 'mlhdlc_replacement_exp';
testbench_name = 'mlhdlc_replacement_exp_tb';
interp_degree = 0;
fixed point converter config
fxpCfg = coder.config('fixpt');
fxpCfg.TestBenchName = 'mlhdlc_replacement_exp_tb';
fxpCfg.TestNumerics = true;
% specify this - for optimized HDL
fxpCfg.DefaultWordLength = 30;
exp - replacement config
mathFcnGenCfg = coder.approximation('log10');
% generally use to increase accuracy; specify this as power of 2 for optimized HDL
% mathFcnGenCfg.NumberOfPoints = 1024;
mathFcnGenCfg.NumberOfPoints = 999999;
mathFcnGenCfg.InterpolationDegree = interp_degree; % can be 0,1,2, or 3
fxpCfg.addApproximation(mathFcnGenCfg);
HDL config object
hdlcfg = coder.config('hdl');
hdlcfg.TargetLanguage = 'Verilog';
hdlcfg.DesignFunctionName = design_name;
hdlcfg.TestBenchName = testbench_name;
hdlcfg.GenerateHDLTestBench=true;
hdlcfg.SimulateGeneratedCode=true;
%If you choose VHDL set the ModelSim compile options as well
hdlcfg.TargetLanguage = 'Verilog';
% hdlcfg.HDLCompileVHDLCmd = 'vcom %s %s -noindexcheck \n';
hdlcfg.ConstantMultiplierOptimization = 'auto'; %optimize out any multipliers from interpolation
hdlcfg.PipelineVariables = 'y u idx_bot x x_idx';%
hdlcfg.InputPipeline = 2;
hdlcfg.OutputPipeline = 2;
hdlcfg.RegisterInputs = true;
hdlcfg.RegisterOutputs = true;
hdlcfg.SynthesizeGeneratedCode = true;
hdlcfg.SynthesisTool = 'Xilinx ISE';
hdlcfg.SynthesisToolChipFamily = 'Virtex7';
hdlcfg.SynthesisToolDeviceName = 'xc7vh580t';
hdlcfg.SynthesisToolPackageName = 'hcg1155';
hdlcfg.SynthesisToolSpeedValue = '-2G';
%codegen('-config',hdlcfg)
codegen('-float2fixed',fxpCfg,'-config',hdlcfg,'mlhdlc_replacement_exp')
%If you only want to do fixed point conversion and stop/examine the
%intermediate results you can use,
%only F2F conversion
codegen('-float2fixed',fxpCfg,'mlhdlc_replacement_exp')

Iniciar sesión para responder a esta pregunta.

Respuestas (0)

Categorías

Más información sobre Simulink Real-Time FPGA I/O Modules en Help Center y File Exchange.

Etiquetas

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by