Unable to fit HDL coder design into FPGA

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John
John le 3 Sep 2025
Commenté : Umar le 6 Sep 2025
I'm having trouble getting the HDL IP core generated by the HDL coder to fit in the FPGA I'm targeting (Cyclone V). I'm using the HDL Workflow Advisor and gets to the step "Build FPGA Bitstream" which launches the quartus build in a separate terminal window. Eventually, Quartus reports this error:
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176218): Packed 1346 registers into blocks of type DSP block
Extra Info (176220): Created 946 register duplicates
Error (184035): Design uses 88 DSP blocks, but only 87 DSP blocks are available in the device
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:23
I have tried going to the HDL block properties of the gain blocks and setting DSPStyle to "off" and I set ConstMultiplierOptimization to "auto". For multiply blocks I also set DSPSyle to "off" and I change the Architecture to "shiftadd". I tried reducing all word lengths to be 16 bits or less. In the HDL Code Generation Optimization settings, I have just about every optimization turned on. Nothing seems to make any difference. It still attempts to use the exact same number of DSP blocks. The only thing that seemed to make a difference is in my custom constraints file I had a directive:
set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS"
but then it used no DSP blocks and then the design was too large because there weren't enough LABs. I need it to be more smart about how it uses the DSP blocks. Does anyone know to properly adjust the settings?
  1 commentaire
Umar
Umar le 3 Sep 2025

Hi @John,

I forgot to add one more important piece in my earlier response — specifically addressing your question:“ Does anyone know to properly adjust the settings? ”

Here are concrete HDL Coder settings worth trying:

1. HDL Workflow Advisor Settings: Enable Resource Sharing for multipliers and adders to reduce DSP duplication. Enable Pipelining to reduce register duplication that often inflates DSP count. Under Multiplier Mapping, allow HDL Coder to automatically select between DSP blocks and logic.

2. Block-Level Settings: Instead of forcing `DSPStyle = off`, leave DSPStyle as auto (or inherit). This allows HDL Coder to decide when to map to DSP vs. logic for best efficiency. For multipliers: Use shift-add only for constant multipliers.

For variable inputs, set architecture back to auto so HDL Coder can use DSP slices more effectively.

3. Word Length Alignment : Ensure multiplier inputs align with Cyclone V DSP block widths (up to 25×18). Even with reduced word lengths (≤16 bits), mismatches can spill across multiple DSPs

4. Constraints: Avoid using `DSP_BLOCK_BALANCING "LOGIC ELEMENTS"` globally, as it pushes everything into LABs. Instead, rely on HDL Coder’s Resource Utilization Report to guide balancing between DSP and logic.

By adjusting these HDL Coder settings systematically, you should be able to better balance DSP vs. logic usage and fit within the Cyclone V resources.

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Umar
Umar le 3 Sep 2025

Hi @John,

I don’t currently have access to Simulink or MATLAB toolboxes to replicate your setup directly, but I reviewed MathWorks documentation and can address your points in order:

Quartus error (88 DSPs used vs. 87 available): This usually occurs when operand sizes don’t align with Cyclone V DSP slice widths. Ensuring multiplier/adder bit widths match native DSP sizes avoids unnecessary extra DSP usage.

`DSPStyle = off` and ConstMultiplierOptimization = auto: Forcing implementation in logic often increases LUT usage. Documentation suggests instead using resource sharing and pipelining optimizations in HDL Coder to balance DSP and logic

Multiply blocks with `shiftadd` architecture: Effective for constant multipliers, but for variable inputs HDL Coder’s multiplier mapping typically provides more efficient DSP utilization

Reducing word lengths ≤16 bits: Helpful, but the bigger factor is operand alignment with DSP slice sizes (e.g., 25×18 multiplies fit neatly into a Cyclone V DSP slice). Mismatches cause multiple DSPs to be consumed.

“Every optimization turned on” in HDL Workflow Advisor: Not all optimizations target DSP balancing. The most impactful are resource sharing and pipelining of arithmetic operations.

Custom constraint `DSP_BLOCK_BALANCING "LOGIC ELEMENTS"`: This forces arithmetic into logic, which explains LAB overflow. Instead, rely on HDL Coder’s internal resource utilization controls for balancing between DSPs and logic.

References (MathWorks docs):

1. [Modeling Efficient Multiplication and Division Operations for FPGA Targeting]( https://www.mathworks.com/help/hdlcoder/ug/modeling-efficient-multiplication-and-division-operations-for-fpga-targeting.html )

2. [Resource Sharing and Streaming Optimizations]( https://www.mathworks.com/help/hdlcoder/ug/resource-sharing-and-streaming-optimizations.html )

3. [Multiplier Mapping Options in HDL Coder]( https://www.mathworks.com/help/hdlcoder/ref/hdlcoder.multipliermapping.html )

4. [Optimize FPGA and ASIC Speed and Area Using HDL Coder]( https://www.mathworks.com/videos/optimize-fpga-and-asic-speed-and-area-using-hdl-coder-1648503804013.html )

5. [HDL Coder Resource Utilization Control]( https://www.mathworks.com/help/hdlcoder/ug/resource-utilization-report.html )

  2 commentaires
John
John le 4 Sep 2025
Thanks for the feedback. The design is now able to fit within the FPGA. It is using 100% of the DSP blocks (87 of 87) and 75% of the LEs. One thing that also seemed to help was I added "set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 80" to my constraints file. Although it shouldn't have made a difference since that has more to do with deivce partitions rather than register packing.
Umar
Umar le 6 Sep 2025

Hi @John,

Great to hear the design now fits! Your MAX_BALANCING_DSP_BLOCKS 80 constraint likely helped indirectly by preventing DSP oversubscription during synthesis.

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