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| author | Alejandro Colomar <alx@kernel.org> | 2024-05-26 20:31:15 +0200 |
|---|---|---|
| committer | Alejandro Colomar <alx@kernel.org> | 2024-05-31 01:37:48 +0200 |
| commit | 5e0dbad3b4d8c4f98e99d515d0de43db3834780f (patch) | |
| tree | ce07f298ad14fe2d2e42f5396761ba24d305f2b2 | |
| parent | 39e3817c72f8109f1aeb6f330e05df95b8bfe2ae (diff) | |
| download | man-pages-5e0dbad3b4d8c4f98e99d515d0de43db3834780f.tar.gz | |
prctl.2, PR_SET_FP_MODE.2const: Split PR_SET_FP_MODE from prctl(2)
Signed-off-by: Alejandro Colomar <alx@kernel.org>
| -rw-r--r-- | man/man2/prctl.2 | 120 | ||||
| -rw-r--r-- | man/man2const/PR_SET_FP_MODE.2const | 147 |
2 files changed, 152 insertions, 115 deletions
diff --git a/man/man2/prctl.2 b/man/man2/prctl.2 index 07e48608d2..0d635d77d9 100644 --- a/man/man2/prctl.2 +++ b/man/man2/prctl.2 @@ -80,118 +80,15 @@ The first argument can be: .B PR_SET_ENDIAN .TQ .B PR_GET_ENDIAN -.\" prctl PR_SET_FP_MODE -.TP -.BR PR_SET_FP_MODE " (since Linux 4.0, only on MIPS)" -.\" commit 9791554b45a2acc28247f66a5fd5bbc212a6b8c8 -On the MIPS architecture, -user-space code can be built using an ABI which permits linking -with code that has more restrictive floating-point (FP) requirements. -For example, user-space code may be built to target the O32 FPXX ABI -and linked with code built for either one of the more restrictive -FP32 or FP64 ABIs. -When more restrictive code is linked in, -the overall requirement for the process is to use the more -restrictive floating-point mode. -.IP -Because the kernel has no means of knowing in advance -which mode the process should be executed in, -and because these restrictions can -change over the lifetime of the process, the +.TQ .B PR_SET_FP_MODE -operation is provided to allow control of the floating-point mode -from user space. -.IP -.\" https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking -The -.I (unsigned int) arg2 -argument is a bit mask describing the floating-point mode used: -.RS -.TP -.B PR_FP_MODE_FR -When this bit is -.I unset -(so called -.BR FR=0 " or " FR0 -mode), the 32 floating-point registers are 32 bits wide, -and 64-bit registers are represented as a pair of registers -(even- and odd- numbered, -with the even-numbered register containing the lower 32 bits, -and the odd-numbered register containing the higher 32 bits). -.IP -When this bit is -.I set -(on supported hardware), -the 32 floating-point registers are 64 bits wide (so called -.BR FR=1 " or " FR1 -mode). -Note that modern MIPS implementations (MIPS R6 and newer) support -.B FR=1 -mode only. -.IP -Applications that use the O32 FP32 ABI can operate only when this bit is -.I unset -.RB ( FR=0 ; -or they can be used with FRE enabled, see below). -Applications that use the O32 FP64 ABI -(and the O32 FP64A ABI, which exists to -provide the ability to operate with existing FP32 code; see below) -can operate only when this bit is -.I set -.RB ( FR=1 ). -Applications that use the O32 FPXX ABI can operate with either -.B FR=0 -or -.BR FR=1 . -.TP -.B PR_FP_MODE_FRE -Enable emulation of 32-bit floating-point mode. -When this mode is enabled, -it emulates 32-bit floating-point operations -by raising a reserved-instruction exception -on every instruction that uses 32-bit formats and -the kernel then handles the instruction in software. -(The problem lies in the discrepancy of handling odd-numbered registers -which are the high 32 bits of 64-bit registers with even numbers in -.B FR=0 -mode and the lower 32-bit parts of odd-numbered 64-bit registers in -.B FR=1 -mode.) -Enabling this bit is necessary when code with the O32 FP32 ABI should operate -with code with compatible the O32 FPXX or O32 FP64A ABIs (which require -.B FR=1 -FPU mode) or when it is executed on newer hardware (MIPS R6 onwards) -which lacks -.B FR=0 -mode support when a binary with the FP32 ABI is used. -.IP -Note that this mode makes sense only when the FPU is in 64-bit mode -.RB ( FR=1 ). -.IP -Note that the use of emulation inherently has a significant performance hit -and should be avoided if possible. -.RE -.IP -In the N32/N64 ABI, 64-bit floating-point mode is always used, -so FPU emulation is not required and the FPU always operates in -.B FR=1 -mode. -.IP -This operation is mainly intended for use by the dynamic linker -.RB ( ld.so (8)). -.IP -The arguments -.IR arg3 , -.IR arg4 , -and -.I arg5 -are ignored. .\" prctl PR_GET_FP_MODE .TP .BR PR_GET_FP_MODE " (since Linux 4.0, only on MIPS)" Return (as the function result) -the current floating-point mode (see the description of -.B PR_SET_FP_MODE +the current floating-point mode +(see +.BR PR_SET_FP_MODE (2const) for details). .IP On success, @@ -2123,14 +2020,6 @@ See .B PR_GET_SPECULATION_CTRL for the bit fields to determine which option is available. .TP -.B EOPNOTSUPP -.I op -is -.B PR_SET_FP_MODE -and -.I arg2 -has an invalid or unsupported value. -.TP .B EPERM .I op is @@ -2214,4 +2103,5 @@ glibc 2.0.6 .BR PR_GET_DUMPABLE (2const), .BR PR_SET_ENDIAN (2const), .BR PR_GET_ENDIAN (2const), +.BR PR_SET_FP_MODE (2const), .BR core (5) diff --git a/man/man2const/PR_SET_FP_MODE.2const b/man/man2const/PR_SET_FP_MODE.2const new file mode 100644 index 0000000000..f5d21c4956 --- /dev/null +++ b/man/man2const/PR_SET_FP_MODE.2const @@ -0,0 +1,147 @@ +.\" Copyright 2016, Eugene Syromyatnikov <evgsyr@gmail.com> +.\" +.\" SPDX-License-Identifier: Linux-man-pages-copyleft +.\" +.TH PR_SET_FP_MODE 2const (date) "Linux man-pages (unreleased)" +.SH NAME +PR_SET_FP_MODE +\- +set the floating point mode of the calling process +.SH LIBRARY +Standard C library +.RI ( libc ", " \-lc ) +.SH SYNOPSIS +.nf +.B #include <sys/prctl.h> +.P +.BI "int prctl(int " op ", ..." +.BI " \fR/*\fP unsigned long " arg2 ", unsigned long " arg3 , +.BI " unsigned long " arg4 ", unsigned long " arg5 " \fR*/\fP );" +.fi +.SH DESCRIPTION +.TP +.BR PR_SET_FP_MODE " (since Linux 4.0, only on MIPS)" +.\" commit 9791554b45a2acc28247f66a5fd5bbc212a6b8c8 +On the MIPS architecture, +user-space code can be built using an ABI which permits linking +with code that has more restrictive floating-point (FP) requirements. +For example, user-space code may be built to target the O32 FPXX ABI +and linked with code built for either one of the more restrictive +FP32 or FP64 ABIs. +When more restrictive code is linked in, +the overall requirement for the process is to use the more +restrictive floating-point mode. +.IP +Because the kernel has no means of knowing in advance +which mode the process should be executed in, +and because these restrictions can +change over the lifetime of the process, the +.B PR_SET_FP_MODE +operation is provided to allow control of the floating-point mode +from user space. +.IP +.\" https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking +The +.I (unsigned int) arg2 +argument is a bit mask describing the floating-point mode used: +.RS +.TP +.B PR_FP_MODE_FR +When this bit is +.I unset +(so called +.BR FR=0 " or " FR0 +mode), the 32 floating-point registers are 32 bits wide, +and 64-bit registers are represented as a pair of registers +(even- and odd- numbered, +with the even-numbered register containing the lower 32 bits, +and the odd-numbered register containing the higher 32 bits). +.IP +When this bit is +.I set +(on supported hardware), +the 32 floating-point registers are 64 bits wide (so called +.BR FR=1 " or " FR1 +mode). +Note that modern MIPS implementations (MIPS R6 and newer) support +.B FR=1 +mode only. +.IP +Applications that use the O32 FP32 ABI can operate only when this bit is +.I unset +.RB ( FR=0 ; +or they can be used with FRE enabled, see below). +Applications that use the O32 FP64 ABI +(and the O32 FP64A ABI, which exists to +provide the ability to operate with existing FP32 code; see below) +can operate only when this bit is +.I set +.RB ( FR=1 ). +Applications that use the O32 FPXX ABI can operate with either +.B FR=0 +or +.BR FR=1 . +.TP +.B PR_FP_MODE_FRE +Enable emulation of 32-bit floating-point mode. +When this mode is enabled, +it emulates 32-bit floating-point operations +by raising a reserved-instruction exception +on every instruction that uses 32-bit formats and +the kernel then handles the instruction in software. +(The problem lies in the discrepancy of handling odd-numbered registers +which are the high 32 bits of 64-bit registers with even numbers in +.B FR=0 +mode and the lower 32-bit parts of odd-numbered 64-bit registers in +.B FR=1 +mode.) +Enabling this bit is necessary when code with the O32 FP32 ABI should operate +with code with compatible the O32 FPXX or O32 FP64A ABIs (which require +.B FR=1 +FPU mode) or when it is executed on newer hardware (MIPS R6 onwards) +which lacks +.B FR=0 +mode support when a binary with the FP32 ABI is used. +.IP +Note that this mode makes sense only when the FPU is in 64-bit mode +.RB ( FR=1 ). +.IP +Note that the use of emulation inherently has a significant performance hit +and should be avoided if possible. +.RE +.IP +In the N32/N64 ABI, 64-bit floating-point mode is always used, +so FPU emulation is not required and the FPU always operates in +.B FR=1 +mode. +.IP +This operation is mainly intended for use by the dynamic linker +.RB ( ld.so (8)). +.IP +The arguments +.IR arg3 , +.IR arg4 , +and +.I arg5 +are ignored. +.SH RETURN VALUE +On success, +0 is returned. +On error, \-1 is returned, and +.I errno +is set to indicate the error. +.SH ERRORS +.TP +.B EOPNOTSUPP +.I op +is +.B PR_SET_FP_MODE +and +.I arg2 +has an invalid or unsupported value. +.SH STANDARDS +Linux. +.SH HISTORY +.SH SEE ALSO +.BR prctl (2), +.BR PR_GET_FP_MODE (2const) |