cocotb: Python-based chip (RTL) verification

Package manager and build abstraction tool for FPGA/ASIC development

Modular hardware build system

An abstraction library for interfacing EDA tools

Style guide enforcement for VHDL

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Repurposing existing HDL tools to help writing better code

HDL symbol generator

Streaming based VHDL parser.

An open-source HDL register code generator fast enough to run in real time.

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

An abstract language model of VHDL written in Python.

hardware library for hwt (= ipcore repo)

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

A package for Sublime Text that aids coding in the VHDL language.

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Configurable AES-GCM IP (128, 192, 256 bits)

A flexible and scalable development platform for modern FPGA projects.

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.