Recently Added - MATLAB Answers

Clear Filters

568 questions found in Answers

Results 151 - 200 of 568

1

answer

0 votes
2 views

Why do I get an error about a missing "thirdpartytools_win64.xml" file when I try to build my model for Xilinx Zynq platform?

Asked by MathWorks Support Team on 21 Jul 2016

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Why am I getting a "SD card is read-only" error during hardware setup for HDL Verifier Support Package for Xilinx FPGA Boards?

Asked by MathWorks Support Team on 10 Jan 2024

Latest activity Answered by MathWorks Support Team on 19 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Adding Xilinx ZCU104 board to SoC Blockset

Asked by Udara De Silva on 26 Jan 2022

Latest activity Edited by Kiran Kintali on 6 Mar 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Find Documentation, Examples and more on HDL Coder Supported Hardware in Help Center

1

answer

0 votes
3 views

Why do I get error messages while installing "HDL Coder Package for RFSoC" in MATLAB R2021b ?

Asked by Jyotirmaya Mohanty on 2 Sep 2023

Latest activity Answered by Wang Chen on 5 Sep 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

probleme of hardware connection in HDL workflow Advisor With the led biking exemple ?

Asked by Sabeha on 6 Mar 2014

Latest activity Answered by Gökhan on 12 Aug 2014

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

I can't find QPSK timing recovery model example built with Simulink® and Xilinx System Generator for DSP™

Asked by Timur Zubov on 27 Jun 2019

Latest activity Answered by Kiran Kintali on 1 Nov 2020

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Find Code on HDL Coder Supported Hardware in File Exchange

1

answer

0 votes
1 view

How to prepare FPGA board for MATLAB

Asked by Thomas on 4 Jun 2014

Latest activity Answered by Kiran Kintali on 24 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices

Asked by chen chen on 24 Jul 2021

Latest activity Answered by Kiran Kintali on 24 Jul 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.

Asked by VISHNU on 3 Nov 2023

Latest activity Answered by Angela Cuadros Castiblanco on 3 Nov 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

1 vote
1 view

Is it possible to get the source code for the Linux kernel that MathWorks uses to create the images for the Zynq support packages?

Asked by MathWorks Support Team on 8 Feb 2021

Latest activity Edited by MathWorks Support Team on 21 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Confused between Hardware to perform Inference

Asked by Aditya on 24 Mar 2024

Latest activity Answered by Kiran Kintali on 24 Mar 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

Trenz Electronic TE0820 support in HDL coder toolbox

Asked by Saulat Chughtai on 15 Feb 2021

Latest activity Edited by Stefanie Schwarz on 18 Aug 2022

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

HDL Advisor Crashing on startup; Error using sdi.Repository/getProperty

Asked by Robert Strunz on 24 Nov 2015

Latest activity Answered by Kiran Kintali on 2 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

What is the difference between HDL coder and System Generator blockset?

Asked by ALEN TOJI VARGHESE on 12 Apr 2021

Latest activity Answered by Kiran Kintali on 1 May 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
10 views

System Generator for Digilent Nexys A7 board with Artix7 100T processor

Asked by SUHANYA M S on 25 Mar 2022

Latest activity Answered by Sachin Lodhi on 28 Feb 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
4 views

i want to convert the following matlab code to verilog code using sysgen. i am new to sysgen.For that what is the procedure to do?

Asked by kokila ayyanar on 12 Feb 2018

Latest activity Edited by Tim McBrayer on 12 Feb 2018

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()

Asked by Yeung Pok Nga on 11 May 2023

Latest activity Commented on by Yeung Pok Nga on 12 May 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

Bitstream Generated through HDL workflow advisor

Asked by Rimsha Javed on 16 May 2023

Latest activity Answered by Sahas on 19 Dec 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

0

answers

0 votes
0 views

Integrating xilinx uartlite driver in simulink

Asked by Saqib Ali on 30 Nov 2018

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

0

answers

0 votes
1 view

HDL Coder bus length interface not appropriate

Asked by Federico Gelmetti on 5 Mar 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Embedded Coder Support Package for Xilinx Zynq Platform cannot connect the laptop to the Zedboard.

Asked by Yuzong Chen on 23 May 2022

Latest activity Answered by Stefanie Schwarz on 22 Sep 2022

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

QPSK transmitter and receiver HDL examples - Why there is no equalization added?

Asked by external on 11 Aug 2023

Latest activity Edited by Ganapathi Subramanian on 29 Aug 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

Installation failure for MATLAB Coder Interface for Deep Learning Libraries and GPU Coder Interface for Deep Learning Libraries support packages in MATLAB R2020b release

Asked by Bill Chou on 17 Nov 2020

Latest activity Answered by Bill Chou on 17 Nov 2020

Accepted Answer by Bill Chou

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

fail to set the hPC.TargetPlatform

Asked by KH on 13 Dec 2024

Latest activity Commented on by KH on 19 Dec 2024

Accepted Answer by KH

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

In HDL Workflow Advisor, why there doesn't exist a platform for ZCU102 and FMCOMMS5?

Asked by Yiping Shi on 24 Mar 2023

Latest activity Commented on by mahan on 5 Jun 2024

Accepted Answer by Parashurama Hosamani

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

HDL work flow advisor for non evaluation board devices

Asked by Anonymous1 on 11 Apr 2022

Latest activity Answered by Kiran Kintali on 16 Jul 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

converting fixed point simulink model to zynq 706

Asked by Hassan Khan on 1 Sep 2021

Latest activity Answered by Kiran Kintali on 7 Oct 2022

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
26 views

HDL Coder Example for ZedBoard

Asked by Dr. W. Kurt Dobson on 9 Feb 2023

Latest activity Commented on by Dr. W. Kurt Dobson on 12 Feb 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
5 views

How to deploy the interface model to SD card of Xilinx Zynq ZCU102 kit so that it will run everytime I power up my hardware ?

Asked by 丹姚 on 30 Jul 2021

Latest activity Answered by JT Ferrara on 2 Aug 2021

Accepted Answer by JT Ferrara

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

Synthesize Matlab function with large input and output onto FPGA

Asked by John Brooks on 3 Jul 2023

Latest activity Edited by Kiran Kintali on 4 Jul 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

How to convert my matlab code having TreeBagger into hdl code using HDL coder

Asked by swetha annangi on 14 Mar 2020

Latest activity Answered by Nishant Gupta on 10 May 2020

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

Matlab and Simulink support for Deepwave Air-T

Asked by Sumanth Raikar on 28 Sep 2021

Latest activity Answered by Swatantra Mahato on 10 Nov 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

The obtained FPGA (Hardware-in-the-loop) output waveform is inconsistent with Simulink simulation results.

Asked by ZhiHao on 17 Sep 2023

Latest activity Commented on by Kiran Kintali on 13 Oct 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
10 views

How do you generate HDL code for the Artix-7 family of boards? What is the recommended workflow for this?

Asked by MathWorks Support Team on 7 Jun 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

0

answers

0 votes
7 views

Sysgen license checkout failed.

Asked by Sandip Paul on 31 Dec 2019

Latest activity Commented on by Ujjwal Jain on 8 Jun 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Deep Learning FPGA Deployment on Xilinx ZCU104

Asked by N/A on 22 Dec 2020

Latest activity Edited by N/A on 3 Jan 2021

Accepted Answer by Shashank Gupta

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
0 views

Xilinx blocks in Simulink

Asked by Krishnakumar on 15 Nov 2013

Latest activity Edited by Tim McBrayer on 26 Nov 2013

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
1 view

Download bit file to Zynq from HDL Coder

Asked by Brent Jarvis on 28 Apr 2017

Latest activity Commented on by zhouwb02 on 8 Jan 2021

Accepted Answer by Tao Jia

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
5 views

How setup Xilinx System Generator in Matlab

Asked by suribright on 13 Aug 2013

Latest activity Edited by Stefanie Schwarz on 26 Jul 2023

Accepted Answer by Kaustubha Govind

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
9 views

unable to download Xilinx Zynq Linux Binaries

Asked by 睿 on 5 Jan 2024

Latest activity Answered by akshatsood on 5 Jan 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

FPGA Synthesis and Analysis HDL Coder

Asked by Shubham on 18 Oct 2024

Latest activity Answered by Sahas on 21 Oct 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Do I have to install a third-party synthesis tool to use HDL Coder?

Asked by MathWorks Support Team on 30 Mar 2021

Latest activity Edited by MathWorks Support Team on 1 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Configuring HDL coder for Xilinx Zynq platform

Asked by Jeffrey Zimmerman on 27 May 2021

Latest activity Answered by Urmila Rajpurohith on 4 Jun 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices

Asked by chen chen on 21 Jul 2021

Latest activity Commented on by chen chen on 24 Jul 2021

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
5 views

up sample Simulink doesn't implement rate convertion on hdl coder

Asked by Raz Elimelech on 20 Jun 2022

Latest activity Answered by Kiran Kintali on 22 Jun 2022

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

HDL Coder "Requested CP number exceeds total number of register-to-register CPs"

Asked by Tom on 16 Apr 2015

Latest activity Commented on by Walter Roberson on 13 Aug 2015

Accepted Answer by Tim McBrayer

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
18 views

Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

Asked by MathWorks Support Team on 17 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

hdl coder hdl verifier: Error on Test Connection

Asked by Dr. W. Kurt Dobson on 13 Feb 2023

Latest activity Commented on by Heman P on 3 Sep 2023

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
2 views

Blocks for HDL Code generation

Asked by SUHANYA M S on 29 Nov 2022

Latest activity Commented on by Bharath Venkataraman on 1 Dec 2022

Accepted Answer by Bharath Venkataraman

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
6 views

How i can import an existing IP Core in Vivado in Simulink as block?

Asked by George Lucian Chiriac on 1 Dec 2021

Latest activity Commented on by SUHANYA M S on 1 Dec 2022

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

Results 151 - 200 of 568

Filter By

Status Clear

Source Clear

Category Clear

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

1

1

2

1

1

1

1

1

1

1

1

1

1

1