VHDL Array Type in entity port

I have been trying to get an array type as an entity port signal. I have simplified it as much as possible.

Package Types is
  Subtype Segment            is std_logic_vector(15 downto 0);
  Type    DataSegment        is array (natural range <>) of Segment;
  Type    DataSegmentType    is array (0 to 4) of Segment;
End Types;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library MyLibrary;
use MyLibrary.Types.all;

Entity MyPort is
  Port (
    pi_clk: in std_logic;
    pi_reset: in std_logic;
    po_myport_data: out std_logic_vector(15 downto 0)
);
End MyPort;

architecture Behavioral of MyPort is

Component UiPort is
  Port (
    pi_clk: in std_logic;
    pi_reset: in std_logic;
    pi_uiport_data: in DataSegment(0 to 2);
    po_uiport_data: out std_logic_vector(15 downto 0)
  );
End Component;

Component UiGoal is
  Port (
    pi_clk: in std_logic;
    pi_reset: in std_logic;
    po_uigoal_data: out std_logic_vector(15 downto 0)
  );
End Component;

--  There are potentially more ui entities here

**signal ls_dataSegment: DataSegment(0 to 2);**

-- The data segment array is the input
-- The process for this entity maps the array inputs to the data output
My_UiPort: UiPort
  Port Map(
    pi_clk => pi_clk, --: in std_logic;
    pi_reset => pi_reset, --: in std_logic;
    pi_uiport_data => ls_dataSegment, --: in DataSegment(0 to 2);
    po_uiport_data => po_myport_data--: out std_logic_vector(15 downto 0)
  );

-- Assign the out port to an element of the array
My_UiGoal: UiGoal
  Port Map(
    pi_clk => pi_clk, --: in std_logic;
    pi_reset => pi_reset, --: in std_logic;
    po_uigoal_data => ls_dataSegment(0) --: out std_logic_vector(15 downto 0)
  );

more instances map other elements of the array

This all seems to synthesize and build, the issue is when UiGoal writes a vector with a '1'in any position the simulator shows the signal as red with x's where the '1's are.

The library is used in all entities.