Defining parameters from command line in (system)verilog simulation

Question

I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module.

As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench.

The idea I had was to launch one simulation for each configuration.

I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override the parameters of the module with the values retrieved from the command-line.

I used $value$plusargs("ARG=%d",val) and the fact that val is a variable is incompatible with the later defparam.

The perfect thing would be to create a define, or a localparam from the command-line argument but I did not find anything about it in my research.

I am also open to any suggestion about another way to doing these simulation, maybe more efficiently, because I think that this will be quite long to do it that way.

PS: To avoid recompiling and re-lauching the simulator for each configuration I also thought about re-instantiating the tested module in each case. I however do not think that it is possible with (system)verilog.

dave_59 · Accepted Answer · 2016-04-05 11:05:57Z

3

Modelsim/Questa allows you to override parameters from the simulation command line, but does so as some cost in simulation performance. Look for the vsim -Gparamname option.

In your case, it would be much better if you could write your modules using variables for these delays instead of parameters, then use $value$plusargs to set them directly.

answered Apr 5, 2016 at 11:05

dave_59

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3 Comments

Krouitch Over a year ago

Thanks, I am using ncsim but I found something similar. Althought, using this option is done during the elaboration. Using argument-passing, I just have to relaunch the simulation right? I guess that it is what make it faster? In fact, the delay is a parametrized delay chain. Does changing the parameter into a variable will work for synthesis?

dave_59 Over a year ago

Delays are not synthesizable

Krouitch Over a year ago

That is not about synthetizing delays, at least not the standard #DELAY ones. I am working with asynchronous designs so I need "real" delays. The "delays" that I am using are delay lines composed of unit delays. Basically a delay line is an array of small buffer driving a large one. However, I cannot do what I want by replacing the parameters by a variable as the parameter is used as an array size, at least not without redesigning the delay line. As one simulations is really quick, ~100ns, I think I will try with the ncelab -DEFPARAM param=val option.

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