Array indexes to wide for array

Question

I have the following problem when accessing arrays in VHDL:

Say I have an array which is not of size 2^n, for example of size 6. Then, if I want to access this array using an index of width 3 bits (=ceil(log2(6))), it is clear that this index can reach two positions, 7 and 8, which are beyond the size of the array I am accessing. Xilinx ISE gives me a warning in this case.

How should I go about this? My possible solutions are as follows:

1.) Ignore the warnings. Hope synthesis is smart.

2.) Only use arrays of size 2^n. Hope unused portions of array will be optimized away.

Jan Decaluwe · Accepted Answer · 2011-02-03 09:23:59Z

3

I suggest to ignore the warnings in this case. Synthesis can handle this.

Synthesis can also easily optimize away anything not used, but artificially increasing array sizes seems like overkill.

answered Feb 3, 2011 at 9:23

Jan Decaluwe

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2 Comments

Philippe Over a year ago

Just a thought: could you just use an "integer range 0 to 5" instead of a 3-bit vector. This might make the simulator happy, and give clear hints to the synthesis tool for optimization.

Jan Decaluwe Over a year ago

@Philippe The simulator would be equally happy or unhappy (in terms of run-time errors) for both cases. But a constrained integer is indeed a more direct way to express the intent.

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