Nested IF in For Loop Verilog

Question

I would like to know if I can put below code in a for loop so I can parameterize my code. Thank you.

always@(*) begin
if (exist_reg[0] == 'd0) begin
    nth_empty_location_descending = 'd1; // specify
end
else if (exist_reg[1] =='d0) begin
    nth_empty_location_descending = 'd2;
end
else if (exist_reg[2] =='d0) begin
    nth_empty_location_descending = 'd4;
end
else if (exist_reg[3] =='d0) begin
    nth_empty_location_descending = 'd8;
end
else if (exist_reg[4] =='d0) begin
    nth_empty_location_descending = 'd16;
end
else if (exist_reg[5] =='d0) begin
    nth_empty_location_descending = 'd32;
end
else if (exist_reg[6] =='d0) begin
    nth_empty_location_descending = 'd64;
end
else if (exist_reg[7] =='d0) begin
    nth_empty_location_descending = 'd128;
end
else if (exist_reg[8] =='d0) begin
    nth_empty_location_descending = 'd256;
end
else if (exist_reg[9] =='d0) begin
    nth_empty_location_descending = 'd512;
end
else begin
    nth_empty_location_descending = 'd0;
end
end

It is basically checking an "exist_reg" bits, if it encounters any bit from left to right is zero then it will rise that bit in "nth_empty_location_descending" register(any better approach?). Now I want to create parameterized code for the width of the register. Currently, it is 10-bit hardcoded code. Thank you experts.

Serge · Accepted Answer · 2018-10-23 15:08:41Z

3

first of all it, the best solution is probably using casez statement instead of the if/else chain:

always@(*) begin
   casez (exist_reg)
     10'b?????????0:  nth_empty_location_descending1 = 'd1;
     10'b????????01:  nth_empty_location_descending1 = 'd2;
     10'b???????011:  nth_empty_location_descending1 = 'd4;
     10'b??????0111:  nth_empty_location_descending1 = 'd8;
     10'b?????01111:  nth_empty_location_descending1 = 'd16;
     10'b????011111:  nth_empty_location_descending1 = 'd32;
     10'b???0111111:  nth_empty_location_descending1 = 'd64;
     10'b??01111111:  nth_empty_location_descending1 = 'd128;
     10'b?011111111:  nth_empty_location_descending1 = 'd256;
     10'b0111111111:  nth_empty_location_descending1 = 'd512;
     default       :  nth_empty_location_descending1 = 'd0;
   endcase // casez (exist_reg)
end // always@ (*)

however, if you insist, there is a loop-based solution:

always @* begin
   nth_empty_location_descending2 = 'd0;

   for (j = 0; j < 10; j = j + 1)  begin
      if (exist_reg[j] == 1'b0) begin
         if (nth_empty_location_descending2 == 0)
           nth_empty_location_descending2 = (10'b1 << j);
      end
   end
end // always @ *

edited Oct 23, 2018 at 15:08

answered Oct 23, 2018 at 15:00

Serge

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1 Comment

user777304 Over a year ago

I thought about casez, but every time width changes I have to add manually new line in case for assignment to nth_empty_location_descending2 register. For loop is the thing I need.

dave_59 · Accepted Answer · 2018-10-23 17:26:14Z

0

parameter WIDTH = 10;
reg [WIDTH-1:0] exist_reg, nth_empty_location_descending2;
integer ii;
always @* begin
   nth_empty_location_descending2 = 0;
   for(ii=0;ii<WIDTH;ii=ii+1)
      if (exist_reg[j] == 1'b0 && nth_empty_location_descending2 == 0)
         nth_empty_location_descending2[ii] = 1'b1;
  end

In SystemVerilog

  parameter WIDTH = 10;
  logic [WIDTH-1:0] exist_reg, nth_empty_location_descending2;
  always_comb begin
     nth_empty_location_descending2 = 0;
     for(int ii=0;ii<WIDTH;ii++)
        if (exist_reg[j] == 1'b0) begin
           nth_empty_location_descending2[ii] = 1'b1;
           break;
        end
    end

edited Oct 23, 2018 at 17:26

answered Oct 23, 2018 at 16:12

dave_59

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