how to initialize an output on verilog (sequential circuit)

Question

I'm new to Verilog coding and I have a college project to design a simple elevator system. The code worked perfectly fine on the FPGA but I cannot get the simulation to work. This is my code:

module move(
    output reg [1:0] current,
    input [1:0] target,
    input clk,
    input overloadin,
    output reg up,
    output reg down
    );

always@(posedge clk)
if (overloadin==1'b0)
begin
if (target[1:0]>current[1:0])
begin
current[1:0] <= current[1:0] + 1;
up = 1'b1;
down = 1'b0;

end
else if (target[1:0]<current[1:0])
begin
current[1:0] <= current[1:0] - 1;
down = 1'b1;
up = 1'b0;

end
else
begin
up = 1'b0;
down = 1'b0;

end
end
endmodule

'current' is declared as wire in the top module. I'm assuming I cannot simulate it because the value of 'current' was not initialized. How can I initialize the value of it without affecting the functionality of the always block?

Oldfart · Accepted Answer · 2018-12-07 13:00:11Z

1

You can use an 'initial' statement or add a reset signal.

initial
   current = 2'b00;

or

  input reset_n,
  ...
   always @(posedge clk or negedge reset_n)
   begin
      if (!reset_n)
         current <= 2'b00;
      else
      ...
   end

I personally prefer the latter but you can find several discussions on the use of initial vs reset in this and the ee forum.

I have not checked the rest of your code because to me it is unreadable due to the lack of indenting.

answered Dec 7, 2018 at 13:00

Oldfart

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Comments

Pradyuman Bissa · Accepted Answer · 2018-12-14 05:35:20Z

you are mixing blocking and non-blocking statements together is causing race condition during simulation. I have modified your code.

module move(
 output reg [1:0] current,
 input [1:0] target,
 input clk,
 input reset_n,             //Added an additional input
 input overloadin,
 output reg up,
 output reg down
);

always@(posedge clk or negedge reset_n)
begin
 if(!reset_n)               //Active low reset
 begin
   up      <= 1'd0;
   down    <= 1'd0;
   current <= 2'd0;
 end
else if(!overloadin)
begin
 if(target > current)
 begin
  up      <= 1'd1;
  down    <= 1'd0;
  current <= current + 2'd1;
 end
 else if(target < current)
 begin
  up      <= 1'd0;
  down    <= 1'd1;
  current <= current - 2'd1;
 end
else
 begin
  up      <= 1'd0;
  down    <= 1'd0;
 end
  end  end  endmodule

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