How to create an array of interface of different size in system verilog

Question

I have a configurable module which contains an interface for one of the ports. I use a generate statement and a for loop to create different configuration of each module instance and I bring the interface ports out in an array. My issue is the individual interfaces are different based of the config of each module instance. Is there a way to configure each interface in the array individually? This is how I correctly configure the interface

test_if    #(.NUM_CUTS(NUM_CUTS_WRITE_CLIENT),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [NUM_OF_MEMS-1:0]();

Is it possible to do something like this with an array of interfaces

test_if    #(.NUM_CUTS(2),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [0]();
test_if    #(.NUM_CUTS(4),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [1]();
test_if    #(.NUM_CUTS(6),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if [2]();

I don't want to have to instantiate each module instance separately outside of the generate statement.

dave_59 · Accepted Answer · 2020-01-06 18:20:35Z

2

You should be able to do this nested inside your generate

for(genvar MEM=0;MEM<NO_OF_MEMS;MEM++) begin : ID
   test_if    #(.NUM_CUTS((MEM+1)*2),.AW(AW_WRITE_CLIENT),.DW(DW_WRITE_CLIENT)) mem_test_if();
end

answered Jan 6, 2020 at 18:20

dave_59

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2 Comments

cgarry Over a year ago

if nest the interface instance within the generate statement, how do access each individual interface instance? Assume NO_OF_MEMS is equal to 5 this gives me interface instances, how can I access each instance outside the generate statement then. Once I have created these separate instances I want to be able to tied them off individually using assign statements

dave_59 Over a year ago

ID[0].mem_test_if, ID[1].mem_test_if, etc. Make sure you give block names to all generated code.

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