How do I generate standalone VHDL or Verilog code with HDL Coder?

Question

MathWorks Support Team 2022-2-5

编辑： MathWorks Support Team 2024-7-17

How can I generate platform-independent standalone VHDL or Verilog code with HDL Coder, without invoking synthesis and implementation in an HDL tool?

I found no "Generate Code Only" option, similar to the one that exists in Simulink Coder for C/C++ code.

Answer 1

编辑：MathWorks Support Team 2024-7-17

In a Simulink model, you have the following additional ways to generate HDL code only, without compiling any code:

Or the "Generate HDL for Subsystem" option from the HDL Coder Block context menu:

You can also use the following settings in the "Workflow Advisor" tool:

Workflow: "Generic ASIC/FPGA"
Synthesis tool: "No synthesis tool available on system path" or "No synthesis tool specified"

From MATLAB:

From Simulink: