For MATLAB R2020a and later releases
Starting in R2020a, you can generate an HDL IP core with multiple AXI4-Stream interfaces, AXI4-Stream Video interfaces, or AXI4 Master interfaces.
To specify more than one AXI4-Stream, AXI4-Stream Video, or AXI4 Master channel, run the IP Core Generation workflow for your Generic Xilinx Platform or Generic Altera Platform. In the Set Target Interface task, on the Target platform interface table, you can then select Add more ... to specify additional Target platform interfaces. After you run this task, the additional interfaces specified are saved on the DUT subsystem as the HDL block property AdditionalTargetInterfaces.
If you are targeting your own custom reference design, in the plugin_rd file, you can specify insertion of multiple AXI4-Stream interfaces and AXI4-Stream Video interfaces by using an addAXI4StreamInterface method and an addAXI4StreamVideoInterface method of the hdlcoder.ReferenceDesign class.
To learn more, see Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces.
For an example, see Running Audio Filter with Multiple AXI4-Stream Channels on ZedBoard.
Workaround for R2019b and prior
As of MATLAB R2019b, HDL Coder only supports one Slave (input) AXI4-Stream interface, and one Master (output) AXI4-Stream interface per IP core.
At this time, a possible workaround is as follows:
1) In HDL Workflow Advisor Task 1.1, it is necessary to select a specific board for "Target platform" (e.g. "Zedboard"). If you select "Generic Xilinx Platform", it is not currently possible to support this workflow
2) Create and register a custom reference design for the selected board. Please run the below command in the command window of installed MATLAB R2019a version to get release specific documentation for this workflow:
To ease this process, you can refer to an existing reference design for the selected board. For example, on a Windows machine the AXI4-Stream reference design for the Zedboard could be found at:
C:\ProgramData\MATLAB\SupportPackages\R2019a\toolbox\hdlcoder\supportpackages\zynq7000\+ZedBoard\+vivado_stream_2018_2
This will also require exporting a block design from Vivado. Please run the below command in the command window of installed MATLAB R2019a version to get release specific documentation for a full example of this workflow:
3) In the custom reference design file (e.g. "plugin_rd.m"), call the "addAXI4StreamInterface" function multiple times to define multiple AXI4-Stream interfaces. Each one of these can be specified with a different Interface ID to distinguish them. For example, you might do the following in your custom reference design file:
% add first AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_1');
% add second AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm_2/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s_2/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_2');
4) Once this custom reference design is created, you can select it in HDL Workflow Advisor Task 1.2.
5) In HDL Workflow Advisor Task 1.3, you can now select from multiple AXI4-Stream interfaces. Note that due to the current limitations, it will be necessary to model and map the READY signals for all the AXI4-Stream interfaces.
