Search results: tag:"hdl coder" - MATLAB Answers

899 questions found in Answers

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Connect AXI4 Master to multiple slaves

Asked by John on 26 Nov 2025 at 18:47

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
6 views

Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""

Asked by Smattacus on 16 Mar 2018

Latest activity Answered by Priyanka on 26 Nov 2025 at 8:47

Code Generation HDL Verifier FPGA Debug FPGA-in-the-Loop

1

answer

0 votes
36 views

Errors when using HDL coder

Asked by Xiaotong on 24 Nov 2025 at 6:32

Latest activity Commented on by Xiaotong on 26 Nov 2025 at 1:28

Code Generation

1

answer

0 votes
7 views

How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?

Asked by Poorren on 14 Sep 2023

Latest activity Commented on by Rud on 19 Nov 2025 at 16:14

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

2

answers

1 vote
18 views

Try to create Vivado project with HDL coder

Asked by hovav dimri on 30 Aug 2023

Latest activity Commented on by Wang Chen on 13 Nov 2025 at 20:57

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
28 views

run Simscape HDL Workflow Advisor from script

Asked by Marco Thommen on 28 Feb 2022

Latest activity Edited by Kiran Kintali on 12 Nov 2025 at 16:29

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design Simscape Hardware-in-the-Loop Workflow

1

answer

0 votes
10 views

generated HDL code failing in cadence AMS

Asked by Rezim on 6 Nov 2025 at 4:36

Latest activity Answered by Kiran Kintali on 6 Nov 2025 at 19:04

Code Generation

1

answer

0 votes
23 views

HDL Coder Error when converting AXI4 interface with different data rates

Asked by John on 4 Nov 2025 at 17:04

Latest activity Commented on by John on 5 Nov 2025 at 15:55

Accepted Answer by Wang Chen

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

2

answers

0 votes
40 views

HDL Coder doesn't complete Testbench Generation

Asked by albs975 on 20 Oct 2025

Latest activity Commented on by albs975 on 3 Nov 2025 at 7:21

Accepted Answer by BA

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

1

answer

0 votes
20 views

Ultra RAM on True Dual Port RAM

Asked by Nick on 23 Dec 2024

Latest activity Commented on by Kiran Kintali on 1 Nov 2025 at 13:15

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

2

answers

2 votes
22 views

How can I force HDL Coder to use DSP48 slices?

Asked by Daniel on 26 Apr 2018

Latest activity Edited by Kiran Kintali on 22 Oct 2025

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

3

answers

0 votes
13 views

Import VHDL in simulink

Asked by MEHN Gildas on 4 Dec 2018

Latest activity Edited by Kiran Kintali on 22 Oct 2025

Code Generation HDL Verifier Algorithm Verification Simulink Cosimulation

1

answer

0 votes
8 views

AXI4 Master Read SDRAM

Asked by John on 6 Oct 2025

Latest activity Commented on by John on 16 Oct 2025

Accepted Answer by Umar

FPGA, ASIC, and SoC Development SoC Blockset System on Chip (SoC)

1

answer

0 votes
6 views

HDL coder generate code from Matlab vs Simulink

Asked by Xiaotong on 13 Oct 2025

Latest activity Answered by Umar on 13 Oct 2025

Accepted Answer by Umar

Code Generation

1

answer

0 votes
7 views

HDL workflow adivsor fails to generate model while using stateflow

Asked by Mohd on 3 Oct 2025

Latest activity Edited by BA on 8 Oct 2025

Accepted Answer by BA

Code Generation

1

answer

2 votes
406 views

Which versions of Vivado are supported with which release of HDL Coder?

Asked by MathWorks Support Team on 16 Apr 2020

Latest activity Edited by MathWorks Support Team on 29 Sep 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Get Started with HDL Coder

1

answer

0 votes
2 views

Sine and Cosine HDL Optimised Block

Asked by Bikki on 23 Sep 2025

Latest activity Answered by Kiran Kintali on 23 Sep 2025

Code Generation

1

answer

0 votes
2 views

Error when using multiple AXI stream interfaces: The specified key is not present in this container

Asked by Alex Alex on 5 Mar 2024

Latest activity Commented on by Martin Ryba on 22 Sep 2025

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
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Regarding HDL_Coder license

Asked by Advaith on 19 Sep 2025

Latest activity Answered by Kiran Kintali on 19 Sep 2025

Code Generation

1

answer

2 votes
17 views

Why is HDL coder not available for home license?

Asked by Alexander Gascoigne on 31 Mar 2017

Latest activity Edited by Nitesh Suryavanshi on 18 Sep 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
1 view

Why does the data capture waveform appear discontinuous?

Asked by 덕용 on 3 Sep 2025

Latest activity Moved by Angelo Yeo on 10 Sep 2025

Accepted Answer by 덕용

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
2 views

Unable to fit HDL coder design into FPGA

Asked by John on 3 Sep 2025

Latest activity Commented on by Umar on 6 Sep 2025

Accepted Answer by Umar

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
3 views

Issues with Device Tree Compilation and FPGA Data Capture on ZedBoard

Asked by 덕용 on 29 Aug 2025

Latest activity Commented on by 덕용 on 5 Sep 2025

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

2

answers

0 votes
5 views

HDL Coder FPGA resources report

Asked by Abel on 14 Aug 2024

Latest activity Commented on by Nhat on 24 Aug 2025

Accepted Answer by Sahas

Code Generation HDL Coder HDL Coder Supported Hardware Speedgoat FPGA I/O Modules

1

answer

0 votes
4 views

Can't find Generate HDL option in filterDesigner Toolbox in MATLAB 2024a

Asked by jialu on 12 Aug 2025

Latest activity Commented on by Bharath Venkataraman on 21 Aug 2025

Signal Processing DSP System Toolbox Code Generation HDL Code Generation

1

answer

0 votes
4 views

Custom Linux build issues

Asked by Malik Sharif on 31 Jul 2025

Latest activity Answered by Sai on 17 Aug 2025

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
4 views

Issues with HDL coder IFFT/FFT Processing with 4x1 Vectors and Data Reordering

Asked by Jina on 10 Apr 2025

Latest activity Answered by Adit on 7 Aug 2025

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

1

answer

0 votes
4 views

Discrepancy between Simulink and hdl code behaviour

Asked by Gary on 31 Jul 2025

Latest activity Commented on by Gary on 7 Aug 2025

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
2 views

How can I connect multiple AXI DMAs to a reference design in HDL Coder?

Asked by MathWorks Support Team on 30 Jun 2025

Latest activity Answered by MathWorks Support Team on 24 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

0

answers

0 votes
2 views

Getting Error while using HDL Coder

Asked by Ashwani on 23 Jun 2025

Latest activity Commented on by Harald on 23 Jul 2025

FPGA, ASIC, and SoC Development

2

answers

0 votes
5 views

FIL Block Output Differs from Expected Value

Asked by Rito Sakima on 10 Jul 2025

Latest activity Answered by Rito Sakima on 23 Jul 2025

Code Generation HDL Verifier FPGA Debug FPGA-in-the-Loop

1

answer

0 votes
6 views

i want to implement 5G NR OFDM system in verilog code using HDL coder

Asked by Shubh on 15 Jul 2025

Latest activity Answered by Kiran Kintali on 16 Jul 2025

Code Generation

1

answer

0 votes
19 views

Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

Asked by MathWorks Support Team on 17 Jun 2019

Latest activity Edited by MathWorks Support Team on 9 Jul 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

¿Thermal Networks compatible with HDL coder?

Asked by JUAN FREDESVINDO RAMOS DELGADO on 19 Aug 2024

Latest activity Answered by Sabin on 4 Jul 2025

Physical Modeling Simscape Electrical

1

answer

0 votes
3 views

Is it feasible to implement a Stanley Controller in FPGA using Simulink and HDL Coder?

Asked by Eden on 11 Apr 2025

Latest activity Answered by Vidhi Agarwal on 2 Jul 2025

Code Generation HDL Coder Get Started with HDL Coder

2

answers

0 votes
10 views

How do I add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder?

Asked by MathWorks Support Team on 4 Apr 2019

Latest activity Edited by MathWorks Support Team on 27 Jun 2025

Accepted Answer by MathWorks Support Team

Code Generation Embedded Coder Deployment, Integration, and Supported Hardware Embedded Coder Supported Hardware Intel SoC Devices

2

answers

0 votes
2 views

Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?

Asked by Sergei on 20 Jun 2025

Latest activity Edited by Sergei on 26 Jun 2025

Accepted Answer by Chandra Adusumalli

Code Generation HDL Coder HDL Coder Supported Hardware Intel SoC Devices

1

answer

0 votes
22 views

Found unsupported division expression for HDL code generation; Signed input data type is not supported for division with Floor RoundMode, at Function 'mod'

Asked by Dumitra on 20 Jun 2025

Latest activity Commented on by Dumitra on 23 Jun 2025

Code Generation

0

answers

0 votes
6 views

SoC Builder Error: The specified key is not present in this container.

Asked by Vu Hoang Thang Chau on 11 Dec 2023

Latest activity Edited by Sergei on 20 Jun 2025

Code Generation

1

answer

0 votes
4 views

Question About Tracking Loop Update Rate in GPS L1 HDL Receiver Example

Asked by Sher on 11 Jun 2025

Latest activity Commented on by Shashikanth Bonamonu on 16 Jun 2025

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

1

answer

0 votes
2 views

How to Implement Configurable Sequence Reordering with N-Way Parallel Outputs Using HDL Coder?

Asked by Matthew on 12 May 2025

Latest activity Edited by Bharath Venkataraman on 3 Jun 2025

FPGA, ASIC, and SoC Development

2

answers

0 votes
10 views

Unable to set Synthesis Attribute on Entity using hdlset_param

Asked by ssourasinth on 30 May 2025

Latest activity Edited by Kiran Kintali on 3 Jun 2025

Code Generation

1

answer

0 votes
3 views

Deep Learning HDL Toolbox with CycloneV SoC board

Asked by Rubén on 13 May 2025

Latest activity Answered by Kiran Kintali on 27 May 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
8 views

How to modify the input ports of the CCSDS LDPC decoder and reduce its BRAM resource consumption

Asked by 玉杰 on 27 Apr 2025

Latest activity Commented on by 玉杰 on 8 May 2025

Accepted Answer by Kranti Balaga

FPGA, ASIC, and SoC Development Wireless HDL Toolbox HDL-Optimized System Design

1

answer

0 votes
4 views

FIL Simulation Failure on Xilinx ZU19EG: "Did not receive version information" Error (MATLAB 2024b + Vivado 2021.2)

Asked by Matthew on 13 Apr 2025

Latest activity Commented on by Matthew on 16 Apr 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
4 views

HDL Coder with Custom IP Core

Asked by John on 2 Apr 2025

Latest activity Commented on by John on 10 Apr 2025

Accepted Answer by Sahas

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
3 views

Read AXI4 address locations from Simulink

Asked by John on 14 Mar 2025

Latest activity Commented on by John on 10 Apr 2025

Accepted Answer by Sahas

Code Generation Embedded Coder Deployment, Integration, and Supported Hardware Embedded Coder Supported Hardware Texas Instruments C2000 Processors

1

answer

0 votes
4 views

Difference in resource utilization using HDL Coder

Asked by Achala G on 1 Apr 2025

Latest activity Answered by Sahas on 9 Apr 2025

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
3 views

data synchronization between two control blocks in simulink

Asked by Gary on 1 May 2024

Latest activity Answered by Rahul on 8 Apr 2025

Code Generation

1

answer

0 votes
1 view

Clarification on Simulink Sample Rate vs HDL Coder Target Frequency

Asked by Jina on 4 Apr 2025

Latest activity Commented on by Jina on 7 Apr 2025

Accepted Answer by Sahas

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

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