When you write code in Verilog on your own the implementation can be different as the code you might have written is more optimized and starightforward to your use. On the other hand, the code generated by MATLAB is fairly generic and less optimized. This is the reason that you can see difference in resourse estimation.
For more information to estimate FPGA resource utilization using MATALB, refer to the following MathWorks documentation on the function "estimateResources": https://www.mathworks.com/help/deep-learning-hdl/ref/dlhdl.processorconfig.estimateresources.html
I hope this is beneficial!
