using variable in for loop to specify index of an array in verilog

Question

I am a newbie in verilog. As variables can not be assigned to index of an array, how I can code this one in verilog, so no compilation error will occur?

module strMatch();

reg [15:0]str;
integer i;

reg [10*8-1:0]searchBuffer;

initial
begin
str = "ab";
searchBuffer = "qwertabjkl";

for (i=10;i>=2;i++)
    begin
   if(searchBuffer[(8*i-1:8*(i-2)]==str[15:0])
       begin
           $display("i");
       end
    end // end of for
end // end of initial

endmodule

Chiggs · Accepted Answer · 2014-04-09 08:59:26Z

1

Firstly you have an extra bracket in your if statement which is causing a syntax error. However even after fixing that your code is still incorrect since you're using i on both sides of your bit selection.

If you're taking a slice, one of the indices has to be constant. Verilog has a special notation for taking a constant range:

if (searchBuffer[8*i+:16]==str[15:0])

This will use 8*i as the base and take a slice of 16 bits. Working example on EDA Playground.

Note there is also a - bit select:

  reg [15:0] big_vect; 
  reg [0:15] little_vect; 

  big_vect[lsb_base_expr    +: width_expr] 
  little_vect[msb_base_expr +: width_expr] 

  big_vect[msb_base_expr    -: width_expr] 
  little_vect[lsb_base_expr -: width_expr]

answered Apr 9, 2014 at 8:59

Chiggs

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