module sobel_CI(a,result,clock);
input clock;
input [31:0] a[0:3];
output [31:0] result;
assign result= a[0]+a[1]+a[2]+a[3];
endmodule
I'm trying to do array declaration in Verilog but it is showing an error:
function argument with unpacked array required systemverilog extensions.
What is wrong with my array?
In Verilog,You can not use multidimensional entity as an input or output, It is allowed in SystemVerilog.
Verilog doesn't allow an I/O port to be a 2-D array.
In Verilog 2001 you could flatten your array into a vector and pass that through the port, but that's somewhat awkward. Here is one way to do it:
module top (in, out);
input [31:0] in;
wire [7:0] array [0:3];
output [31:0] out;
assign {array[3],array[2],array[1],array[0]} = in;
assign out = {array[3],array[2],array[1],array[0]};
endmodule
